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From: | Richard Henderson |
Subject: | Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension |
Date: | Fri, 15 Oct 2021 17:01:20 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
On 10/15/21 12:29 PM, Alexey Baturo wrote:
FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) +/* If PointerMasking should be applied */ +FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
Merge error.
+ if (riscv_has_ext(env, RVJ)) { + int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
cpu_mmu_index has already been computed. You want int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
@@ -118,16 +125,6 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); }-/*- * Temp stub: generates address adjustment for PointerMasking - */ -static void gen_pm_adjust_address(DisasContext *s, - TCGv *dst, - TCGv src) -{ - tcg_gen_mov_tl(*dst, src); -} -
You might as well place the function correctly in the previous patch. Drop the silly alignment of parameters.
+ int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK; + ctx->pm_mask = pm_mask[priv];
Using cpu_mmu_index within the translator is incorrect. You want priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; r~
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