Re: [PATCH 11/13] target/riscv: Adjust trans_rev8

qemu-riscv

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Re: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64

From:	LIU Zhiwei
Subject:	Re: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
Date:	Wed, 13 Oct 2021 19:45:34 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 2021/10/8 上午1:47, Richard Henderson wrote:

When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>

Zhiwei

---
  target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }

+static void gen_rev8_32(TCGv ret, TCGv src1)

+{
+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
  static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
  {
      REQUIRE_32BIT(ctx);
      REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
  }

static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)

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[PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, (continued)
- [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/07
  - Re: [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, LIU Zhiwei, 2021/10/13
- [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/07
- [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/07
  - Re: [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB, LIU Zhiwei, 2021/10/13
- [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/07
- [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/07
- [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/07
- [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/07
- [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/07
  - Re: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, LIU Zhiwei <=
- [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/07
  - Re: [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM, LIU Zhiwei, 2021/10/13
- Re: [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length, Frédéric Pétrot, 2021/10/10

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