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[PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shif
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From: |
Frédéric Pétrot |
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Subject: |
[PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers |
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Date: |
Wed, 6 Oct 2021 23:28:17 +0200 |
The code generation helpers are now able to handle also the 128-bit
functions, although no such function exists yet.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 102 +++++++++++++++++++++++++++++++++------
1 file changed, 88 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9a74abecdd..b3f70bcde0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -442,11 +442,14 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
- /* Temporary code so that the patch compiles */
if (is_128bit(ctx)) {
- (void)get_gprh(ctx, 6);
- (void)dest_gprh(ctx, 6);
- gen_set_gprh(ctx, 6, NULL);
+ uint64_t immh = -(a->imm < 0);
+ src1 = get_gprh(ctx, a->rs1);
+ dest = dest_gprh(ctx, a->rd);
+
+ func(dest, src1, immh);
+
+ gen_set_gprh(ctx, a->rd, dest);
}
return true;
@@ -463,6 +466,15 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ if (is_128bit(ctx)) {
+ dest = dest_gprh(ctx, a->rd);
+ src1 = get_gprh(ctx, a->rs1);
+ src2 = get_gprh(ctx, a->rs2);
+
+ func(dest, src1, src2);
+
+ gen_set_gprh(ctx, a->rd, dest);
+ }
return true;
}
@@ -485,8 +497,16 @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
DisasExtend ext,
fn64(dest, src1, a->imm);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ fn128(destl, desth, src1l, src1h, a->imm);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -512,8 +532,18 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd),
+ imml = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0));
+
+ fn128(destl, desth, src1l, src1h, imml, immh);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -540,8 +570,21 @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, ext),
+ src2h = get_gprh(ctx, a->rs2),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, src2l, src2h);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -579,8 +622,24 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift
*a, DisasExtend ext,
fn64(dest, src1, a->shamt);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ if ((ctx->w && a->shamt >= 32)
+ || (!ctx->w && a->shamt >= 128)) {
+ return false;
+ }
+
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -632,8 +691,23 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free(ext2);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new(),
+ shamt = tcg_temp_new();
+
+ tcg_gen_andi_tl(shamt, src2l, !ctx->w << 5 | 0x1f);
+ fn128(destl, desth, src1l, src1h, shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
+ tcg_temp_free(shamt);
}
return true;
}
--
2.33.0
- Re: [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values, (continued)
- [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa, Frédéric Pétrot, 2021/10/06
- [PATCH v2 05/27] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/06
- [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers,
Frédéric Pétrot <=
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 16/27] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/06
- [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 13/27] target/riscv: rename a few gen function helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic, Frédéric Pétrot, 2021/10/06
- [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit, Frédéric Pétrot, 2021/10/06
- [PATCH v2 22/27] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/06