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[PATCH v2 05/27] target/riscv: additional macros to check instruction su
From: |
Frédéric Pétrot |
Subject: |
[PATCH v2 05/27] target/riscv: additional macros to check instruction support |
Date: |
Wed, 6 Oct 2021 23:28:11 +0200 |
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3c929ce960..96a1e40606 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -357,11 +357,29 @@ EX_SH(12)
} while (0)
#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
+ if (!is_64bit(ctx)) { \
return false; \
} \
} while (0)
+#define REQUIRE_128BIT(ctx) do { \
+ if (!is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_32_OR_64BIT(ctx) do { \
+ if (is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_64_OR_128BIT(ctx) do { \
+ if (is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.33.0
- [PATCH v2 00/27] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/06
- [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/06
- [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa, Frédéric Pétrot, 2021/10/06
- [PATCH v2 05/27] target/riscv: additional macros to check instruction support,
Frédéric Pétrot <=
- [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/06
- [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 16/27] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/06