Re: [PATCH v4 00/21] target/riscv: Use tcg_constant_*

[Alistair Francis]

On Sat, Aug 21, 2021 at 3:43 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Replace use of tcg_const_*, which makes a copy into a temp which must
> be freed, with direct use of the constant.  Reorg handling of $zero,
> with different accessors for source and destination.  Reorg handling
> of csrs, passing the actual write_mask instead of a regno.  Use more
> helpers for RVH expansion.
>
> Patches lacking review:
>   02-tests-tcg-riscv64-Add-test-for-division.patch
>   03-target-riscv-Clean-up-division-helpers.patch
>   11-target-riscv-Add-DisasExtend-to-gen_unary.patch
>   17-target-riscv-Use-gen_shift_imm_fn-for-slli_uw.patch
>   21-target-riscv-Use-get-dest-_gpr-for-RVV.patch

This should be all reviewed now. Do you want me to take it or do you plan on it?

Alistair

>
> Changes for v4:
>   * Add a test for division, primarily checking the edge cases.
>   * Dropped the greviw patch, since grev has been dropped from Zbb 1.0.0.
>
> Changes for v3:
>   * Fix an introduced remainder bug (bin meng),
>     and remove one extra movcond from rem/remu.
>   * Do not zero DisasContext on allocation (bin meng).
>
> Changes for v2:
>   * Retain the requirement to call gen_set_gpr.
>   * Add DisasExtend as an argument to get_gpr, and ctx->w as a member
>     of DisasContext.  This should help in implementing UXL, where we
>     should be able to set ctx->w for all insns, but there is certainly
>     more required for that.
>
> r~
>
>
> Richard Henderson (21):
>   target/riscv: Use tcg_constant_*
>   tests/tcg/riscv64: Add test for division
>   target/riscv: Clean up division helpers
>   target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
>   target/riscv: Introduce DisasExtend and new helpers
>   target/riscv: Add DisasExtend to gen_arith*
>   target/riscv: Remove gen_arith_div*
>   target/riscv: Use gen_arith for mulh and mulhu
>   target/riscv: Move gen_* helpers for RVM
>   target/riscv: Move gen_* helpers for RVB
>   target/riscv: Add DisasExtend to gen_unary
>   target/riscv: Use DisasExtend in shift operations
>   target/riscv: Use get_gpr in branches
>   target/riscv: Use {get,dest}_gpr for integer load/store
>   target/riscv: Reorg csr instructions
>   target/riscv: Use {get,dest}_gpr for RVA
>   target/riscv: Use gen_shift_imm_fn for slli_uw
>   target/riscv: Use {get,dest}_gpr for RVF
>   target/riscv: Use {get,dest}_gpr for RVD
>   target/riscv: Tidy trans_rvh.c.inc
>   target/riscv: Use {get,dest}_gpr for RVV
>
>  target/riscv/helper.h                   |   6 +-
>  target/riscv/insn32.decode              |   1 +
>  target/riscv/op_helper.c                |  18 +-
>  target/riscv/translate.c                | 701 ++++++------------------
>  tests/tcg/riscv64/test-div.c            |  58 ++
>  target/riscv/insn_trans/trans_rva.c.inc |  51 +-
>  target/riscv/insn_trans/trans_rvb.c.inc | 370 ++++++++++---
>  target/riscv/insn_trans/trans_rvd.c.inc | 127 +++--
>  target/riscv/insn_trans/trans_rvf.c.inc | 149 +++--
>  target/riscv/insn_trans/trans_rvh.c.inc | 266 ++-------
>  target/riscv/insn_trans/trans_rvi.c.inc | 360 ++++++------
>  target/riscv/insn_trans/trans_rvm.c.inc | 191 +++++--
>  target/riscv/insn_trans/trans_rvv.c.inc | 151 ++---
>  tests/tcg/riscv64/Makefile.target       |   5 +
>  14 files changed, 1125 insertions(+), 1329 deletions(-)
>  create mode 100644 tests/tcg/riscv64/test-div.c
>  create mode 100644 tests/tcg/riscv64/Makefile.target
>
> --
> 2.25.1
>
>