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[PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw
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From: |
Richard Henderson |
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Subject: |
[PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw |
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Date: |
Fri, 20 Aug 2021 07:42:53 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index b97c3ca5da..74cb93a2db 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -635,21 +635,18 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
}
+static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+{
+ if (shamt < 32) {
+ tcg_gen_deposit_z_tl(dest, src, shamt, 32);
+ } else {
+ tcg_gen_shli_tl(dest, src, shamt);
+ }
+}
+
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
-
- TCGv source1 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
-
- if (a->shamt < 32) {
- tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
- } else {
- tcg_gen_shli_tl(source1, source1, a->shamt);
- }
-
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- return true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
--
2.25.1
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, (continued)
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/20
- [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/20
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- [PATCH v4 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/20
- [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/20
- [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw,
Richard Henderson <=
- [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20
- [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/20
- [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/20
- [PATCH v4 19/21] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/20
- [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/20
- [PATCH v4 21/21] target/riscv: Use {get,dest}_gpr for RVV, Richard Henderson, 2021/08/20
- Re: [PATCH v4 00/21] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/30