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Re: [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations


From: Bin Meng
Subject: Re: [PATCH v2 11/21] target/riscv: Use DisasExtend in shift operations
Date: Thu, 19 Aug 2021 14:13:24 +0800

On Wed, Aug 18, 2021 at 5:26 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These operations are greatly simplified by ctx->w, which allows
> us to fold gen_shiftw into gen_shift.  Split gen_shifti into
> gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/translate.c                | 110 +++++++++-----------
>  target/riscv/insn_trans/trans_rvb.c.inc | 129 +++++++++++-------------
>  target/riscv/insn_trans/trans_rvi.c.inc |  88 ++++------------
>  3 files changed, 125 insertions(+), 202 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>



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