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Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruct
From: |
LIU Zhiwei |
Subject: |
Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction |
Date: |
Thu, 24 Jun 2021 14:05:46 +0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 2021/6/11 上午3:39, Richard Henderson
wrote:
On
6/10/21 12:58 AM, LIU Zhiwei wrote:
include/tcg/tcg-op-gvec.h
| 6 ++
tcg/tcg-op-gvec.c | 47 ++++++++++++++++
Likewise, should be split from the larger patch.
+static void gen_addv_mask_i32(TCGv_i32 d,
TCGv_i32 a, TCGv_i32 b, TCGv_i32 m)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+
+ tcg_gen_andc_i32(t1, a, m);
+ tcg_gen_andc_i32(t2, b, m);
+ tcg_gen_xor_i32(t3, a, b);
+ tcg_gen_add_i32(d, t1, t2);
+ tcg_gen_and_i32(t3, t3, m);
+ tcg_gen_xor_i32(d, d, t3);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+}
+
+void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8,
0x80));
+ gen_addv_mask_i32(d, a, b, m);
+}
There will only ever be one use; we might as well merge them.
OK
The
cast is unnecessary.
I meet compiler error report without cast. So I just keep it.
../tcg/tcg-op-gvec.c: In function ‘tcg_gen_vec_sub8_i32’:
/home/roman/git/qemu/include/tcg/tcg.h:1327:5: error: overflow in implicit constant conversion [-Werror=overflow]
(__builtin_constant_p(VECE) \
^
../tcg/tcg-op-gvec.c:1947:35: note: in expansion of macro ‘dup_const’
TCGv_i32 m = tcg_constant_i32(dup_const(MO_8, 0x80));
^~~~~~~~~
cc1: all warnings being treated as errors
Thanks,
Zhiwei
r~
- [PATCH v2 00/37] target/riscv: support packed extension v0.9.4, LIU Zhiwei, 2021/06/10
- [PATCH v2 01/37] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2021/06/10
- [PATCH v2 02/37] target/riscv: Make the vector helper functions public, LIU Zhiwei, 2021/06/10
- [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/06/10
- [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 06/37] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 10/37] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/06/10