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[PATCH v2 37/37] target/riscv: configure and turn on packed extension fr
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line |
Date: |
Thu, 10 Jun 2021 15:59:08 +0800 |
Packed extension is default off. The only way to use packed extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv32,x-p=true,Zpsfoperand=true,pext_spec=v0.9.4".
Zpsfoperand is whether to support Zpsfoperand sub-extension,
default value is true.
pext_ver is the packed specification version, default value is v0.9.4.
These properties can be specified with other values.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9d8cf60a1c..21020b902e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,14 +618,17 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+ DEFINE_PROP_BOOL("x-p", RISCVCPU, cfg.ext_p, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
+ DEFINE_PROP_STRING("pext_spec", RISCVCPU, cfg.pext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("Zpsfoperand", RISCVCPU, cfg.ext_psfoperand, true),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.25.1
- [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions, (continued)
- [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line,
LIU Zhiwei <=
- Re: [PATCH v2 00/37] target/riscv: support packed extension v0.9.4, no-reply, 2021/06/14