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[PATCH RFC v5 12/12] target/riscv: Support virtual time context synchron
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From: |
Yifei Jiang |
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Subject: |
[PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization |
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Date: |
Mon, 12 Apr 2021 14:52:46 +0800 |
Add virtual time context description to vmstate_riscv_cpu. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 44d4015bd6..ef2d5395a8 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -138,10 +138,20 @@ static const VMStateDescription vmstate_hyper = {
}
};
+static int cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ env->kvm_timer_dirty = true;
+ return 0;
+}
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
+ .post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -185,6 +195,10 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT64(env.mtohost, RISCVCPU),
VMSTATE_UINT64(env.timecmp, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
--
2.19.1
- Re: [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers, (continued)
- [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 09/12] target/riscv: Add host cpu type, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization,
Yifei Jiang <=