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Re: [RFC v4 22/70] target/riscv: rvv-1.0: amo operations
From: |
Richard Henderson |
Subject: |
Re: [RFC v4 22/70] target/riscv: rvv-1.0: amo operations |
Date: |
Sat, 29 Aug 2020 11:50:17 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +static bool vext_check_amo(DisasContext *s, int vd, int vs2,
> + int wd, int vm, uint8_t eew)
> +{
> + int8_t emul = ctzl(eew) - (s->sew + 3) + s->lmul;
> + bool ret = has_ext(s, RVA) &&
> + (1 << s->sew >= 4) &&
> + (1 << s->sew <= sizeof(target_ulong)) &&
> + (eew <= (sizeof(target_ulong) << 3)) &&
> + require_align(vd, 1 << s->lmul) &&
> + require_align(vs2, 1 << emul) &&
> + (emul >= -3 && emul <= 3);
> + if (wd) {
> + ret &= require_vm(vm, vd);
> + if (eew > (1 << (s->sew + 3))) {
> + if (vd != vs2) {
> + ret &= require_noover(vd, 1 << s->lmul, vs2, 1 << emul);
> + }
> + } else if (eew < (1 << (s->sew + 3))) {
> + if (emul < 0) {
> + ret &= require_noover(vd, 1 << s->lmul, vs2, 1 << emul);
> + } else {
> + ret &= require_noover_widen(vd, 1 << s->lmul, vs2, 1 <<
> emul);
> + }
> + }
> + }
> + return ret;
> +}
Same comments for EEW and require_noover.
r~
- [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions, (continued)
- [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/08/17
- [RFC v4 18/70] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/08/17
- [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/17
- [RFC v4 20/70] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/17
- [RFC v4 21/70] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/17
- [RFC v4 22/70] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/17
- Re: [RFC v4 22/70] target/riscv: rvv-1.0: amo operations,
Richard Henderson <=
- [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/17
- [RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/17
- [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/17
- [RFC v4 26/70] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/17
- [RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/17
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/17
- [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/17