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Re: [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructi
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions |
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Date: |
Sat, 29 Aug 2020 11:33:52 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
> + uint8_t eew)
> {
> - return !s->vill;
> + uint8_t lmul_r = s->lmul < 0 ? 0 : s->lmul;
> + int8_t emul = ctzl(eew) - (s->sew + 3) + s->lmul;
> + return (emul >= -3 && emul <= 3) &&
> + require_align(vs2, 1 << emul) &&
> + require_align(vd, 1 << s->lmul) &&
> + ((nf << lmul_r) <= (NVPR / 4) &&
> + (vd + (nf << lmul_r)) <= NVPR);
> +}
Same comments wrt EEW as the last patch.
It wouldn't hurt to extract something like
static bool require_nf(int vd, int nf, int lmul)
{
int size = nf << MAX(lmul, 0);
return size <= 8 && vd + size <= 32;
}
in the previous patch as well.
r~
- Re: [RFC v4 14/70] target/riscv: rvv-1.0: update check functions, (continued)
- [RFC v4 13/70] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/17
- [RFC v4 15/70] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/17
- [RFC v4 16/70] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/08/17
- [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/08/17
- [RFC v4 18/70] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/08/17
- [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/17
- Re: [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions,
Richard Henderson <=
- [RFC v4 20/70] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/17
- [RFC v4 21/70] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/17
- [RFC v4 22/70] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/17
- [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/17
- [RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/17