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[PATCH v2 02/16] hw/riscv: hart: Add a new 'resetvec' property
From: |
Bin Meng |
Subject: |
[PATCH v2 02/16] hw/riscv: hart: Add a new 'resetvec' property |
Date: |
Sat, 29 Aug 2020 23:17:26 +0800 |
From: Bin Meng <bin.meng@windriver.com>
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/riscv_hart.h | 1 +
hw/riscv/riscv_hart.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index c75856f..77aa4bc 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
uint32_t num_harts;
uint32_t hartid_base;
char *cpu_type;
+ uint64_t resetvec;
RISCVCPU *harts;
} RISCVHartArrayState;
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index f59fe52..613ea2a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+ DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+ DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
@@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int
idx,
char *cpu_type, Error **errp)
{
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
--
2.7.4
- [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Bin Meng, 2020/08/29
- [PATCH v2 01/16] target/riscv: cpu: Add a new 'resetvec' property, Bin Meng, 2020/08/29
- [PATCH v2 02/16] hw/riscv: hart: Add a new 'resetvec' property,
Bin Meng <=
- [PATCH v2 03/16] target/riscv: cpu: Set reset vector based on the configured property value, Bin Meng, 2020/08/29
- [PATCH v2 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board, Bin Meng, 2020/08/29
- [PATCH v2 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation, Bin Meng, 2020/08/29
- [PATCH v2 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs, Bin Meng, 2020/08/29
- [PATCH v2 07/16] hw/sd: Add Cadence SDHCI emulation, Bin Meng, 2020/08/29
- [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Bin Meng, 2020/08/29
- [PATCH v2 09/16] hw/dma: Add SiFive platform DMA controller emulation, Bin Meng, 2020/08/29
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller, Bin Meng, 2020/08/29
- [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property, Bin Meng, 2020/08/29
- [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23, Bin Meng, 2020/08/29