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[RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum
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From: |
frank . chang |
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Subject: |
[RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum |
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Date: |
Mon, 17 Aug 2020 16:49:47 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.inc.c | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index bb346a82499..92e076c6ed8 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 4f33c42990e..c148ed40c9f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2430,7 +2430,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2510,7 +2510,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2542,7 +2542,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2578,7 +2578,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2608,7 +2608,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2644,7 +2644,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2721,7 +2721,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2862,7 +2862,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2908,7 +2908,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index bca48297dab..d9ea6a32188 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+enum {
+ FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ FRM_RTZ = 1, /* Round towards Zero */
+ FRM_RDN = 2, /* Round Down */
+ FRM_RUP = 3, /* Round Up */
+ FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
- Re: [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction, (continued)
- [RFC v4 56/70] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2020/08/17
- [RFC v4 57/70] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/08/17
- [RFC v4 58/70] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/08/17
- [RFC v4 59/70] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2020/08/17
- [RFC v4 61/70] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2020/08/17
- [RFC v4 60/70] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/08/17
- [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum,
frank . chang <=
- [RFC v4 63/70] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/08/17
- [RFC v4 64/70] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/08/17
- [RFC v4 66/70] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 67/70] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits, frank . chang, 2020/08/17