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Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path


From: Bin Meng
Subject: Re: [PATCH 1/3] riscv: Unify Qemu's reset vector code path
Date: Thu, 18 Jun 2020 16:02:33 +0800

On Wed, Jun 17, 2020 at 3:30 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Currently, all riscv machines have identical reset vector code
> implementations with memory addresses being different for all machines.
> They can be easily combined into a single function in common code.
>
> Move it to common function and let all the machines use the common function.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  hw/riscv/boot.c         | 46 +++++++++++++++++++++++++++++++++++++++++
>  hw/riscv/sifive_u.c     | 38 +++-------------------------------

sifive_u's reset vector has to be different to emulate the real
hardware MSEL pin state.
Please rebase this on top of the following series:
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=183567

>  hw/riscv/spike.c        | 38 +++-------------------------------
>  hw/riscv/virt.c         | 37 +++------------------------------
>  include/hw/riscv/boot.h |  2 ++
>  5 files changed, 57 insertions(+), 104 deletions(-)
>

Regards,
Bin



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