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Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 |
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Date: |
Thu, 18 Jun 2020 08:41:43 +0800 |
Hi Alistair,
On Thu, Jun 18, 2020 at 12:40 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Per the SiFive manual, all E/U series CPU cores' reset vector is
> > at 0x1004. Update our codes to match the hardware.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> This commit breaks my Oreboot test.
>
> Oreboot starts in flash and we run the command with the
> `sifive_u,start-in-flash=true` machine.
Could you please post an Oreboot binary for testing somewhere, or some
instructions so that I can test this?
>
> I have removed this and the later patches from the RISC-V branch. I
> want to send a PR today. After that I'll look into this.
Regards,
Bin
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries, Bin Meng, 2020/06/15
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/15
[PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Bin Meng, 2020/06/15
Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support, Alistair Francis, 2020/06/16