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Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code
From: |
Alistair Francis |
Subject: |
Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit |
Date: |
Mon, 15 Jun 2020 09:07:26 -0700 |
On Mon, Jun 8, 2020 at 7:19 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to retrieve all PLIC IRQ information in order to
> just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
> what is done for other peripherals.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f9fef2b..cf7f833 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -528,7 +528,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
> **errp)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> - qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
> char *plic_hart_config;
> size_t plic_hart_config_len;
> int i;
> @@ -612,10 +611,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
> **errp)
> object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
>
> - for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
> - plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
> - }
> -
> if (nd->used) {
> qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
> qdev_set_nic_properties(DEVICE(&s->gem), nd);
> @@ -629,7 +624,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
> **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
> - plic_gpios[SIFIVE_U_GEM_IRQ]);
> + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> --
> 2.7.4
>
>
- [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support, Bin Meng, 2020/06/08
- [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Bin Meng, 2020/06/08
- [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Bin Meng, 2020/06/08
- [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP, Bin Meng, 2020/06/08
- [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Bin Meng, 2020/06/08
- Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit,
Alistair Francis <=
- [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Bin Meng, 2020/06/08
- [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes, Bin Meng, 2020/06/08
- [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Bin Meng, 2020/06/08
- [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller, Bin Meng, 2020/06/08
- [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality, Bin Meng, 2020/06/08