Re: [PATCH v2] riscv: Add helper to make NaN-boxing for FP register

[Alistair Francis]

On Tue, Jun 9, 2020 at 3:08 AM Chih-Min Chao <chihmin.chao@sifive.com> wrote:
>
> ping ?  Could this be merged ?

Applied to the RISC-V tree.

Alistair

>
>
> Chih-Min Chao
>
>
>
> On Wed, Jan 29, 2020 at 3:43 AM Richard Henderson 
> <richard.henderson@linaro.org> wrote:
>>
>> On 1/27/20 4:37 PM, Ian Jiang wrote:
>> > The function that makes NaN-boxing when a 32-bit value is assigned
>> > to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
>> > Then it is applied in translating of the FLW instruction.
>> >
>> > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
>> > ---
>> >  target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++--
>> >  1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>
>>
>> r~
>>