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Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding
From: |
Richard Henderson |
Subject: |
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes |
Date: |
Thu, 4 Jun 2020 13:15:16 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 6/2/20 10:46 PM, LIU Zhiwei wrote:
> I think you are right. Maybe I should transmit frm to ctx->frm, and check
> ctx->frm in vector fp ops.
>
> We can set ctx->frm = env->frm instead of ctx->frm = -1 in
> riscv_tr_init_disas_context.
> And remove the sentence ctx->frm = rm; from gen_set_rm.
>
> Is it right?
If we record frm in tb_flags, then we also have to reset
env->fp_status.rounding_mode for scalar fp insns which encode a rm != 7.
Depending on the exact mix of fp insns, that could result in more changes to
rounding_mode than we do presently. This is something that you'd want to look
at closely to make sure you're not making scalar code worse.
I think the easiest solution in the short term is to have the translation of
any fp vector insn call gen_set_rm(ctx, 7), so that we are certain to install
frm as rounding_mode. This will happen at most once per translation block,
assuming no scalar insns that would also require changes to rounding_mode.
You can work with the risc-v folk to examine frm handling more generally
separate from this vector work.
r~