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[PULL 24/34] target/ppc: Move mffsl to decodetree
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 24/34] target/ppc: Move mffsl to decodetree |
Date: |
Wed, 6 Jul 2022 17:09:36 -0300 |
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220629162904.105060-5-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fp-impl.c.inc | 38 +++++++++++++-----------------
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 7cb7faabac..6b68689357 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -345,6 +345,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 -
@X_bi
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
+MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
### Decimal Floating-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 64e26b9b42..4f4d57c611 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -633,28 +633,6 @@ static void gen_mffs(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
-/* mffsl */
-static void gen_mffsl(DisasContext *ctx)
-{
- TCGv_i64 t0;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- /* Mask everything except mode, status, and enables. */
- tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
{
TCGv_i64 fpscr = tcg_temp_new_i64();
@@ -739,6 +717,22 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2
*a)
return true;
}
+static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
+{
+ TCGv_i64 fpscr;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt,
+ FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN);
+
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
/* mtfsb0 */
static void gen_mtfsb0(DisasContext *ctx)
{
diff --git a/target/ppc/translate/fp-ops.c.inc
b/target/ppc/translate/fp-ops.c.inc
index a76943b8bf..f8c35124ae 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -75,8 +75,6 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE,
PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
-GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
--
2.36.1
- [PULL 20/34] ppc/spapr: Implement H_WATCHDOG, (continued)
- [PULL 20/34] ppc/spapr: Implement H_WATCHDOG, Daniel Henrique Barboza, 2022/07/06
- [PULL 19/34] ppc: Define SETFIELD for the ppc target, Daniel Henrique Barboza, 2022/07/06
- [PULL 16/34] target/ppc: use int128.h methods in vsubuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 14/34] target/ppc: use int128.h methods in vaddecuq and vaddeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 12/34] target/ppc: use int128.h methods in vpmsumd, Daniel Henrique Barboza, 2022/07/06
- [PULL 13/34] target/ppc: use int128.h methods in vadduqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 21/34] target/ppc: Fix insn32.decode style issues, Daniel Henrique Barboza, 2022/07/06
- [PULL 18/34] target/ppc: use int128.h methods in vsubcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 17/34] target/ppc: use int128.h methods in vsubecuq and vsubeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 15/34] target/ppc: use int128.h methods in vaddcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 24/34] target/ppc: Move mffsl to decodetree,
Daniel Henrique Barboza <=
- [PULL 29/34] target/ppc: implement addg6s, Daniel Henrique Barboza, 2022/07/06
- [PULL 25/34] target/ppc: Move mffs[.] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 22/34] target/ppc: Move mffscrn[i] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions, Daniel Henrique Barboza, 2022/07/06
- [PULL 27/34] tests/tcg/ppc64: Add mffsce test, Daniel Henrique Barboza, 2022/07/06
- [PULL 23/34] target/ppc: Move mffsce to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 26/34] target/ppc: Implement mffscdrn[i] instructions, Daniel Henrique Barboza, 2022/07/06
- [PULL 30/34] target/ppc: implement cbcdtd, Daniel Henrique Barboza, 2022/07/06
- [PULL 31/34] target/ppc: implement cdtbcd, Daniel Henrique Barboza, 2022/07/06
- [PULL 33/34] target/ppc/cpu-models: Remove the "default" CPU alias, Daniel Henrique Barboza, 2022/07/06