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[PULL 18/34] target/ppc: use int128.h methods in vsubcuq
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 18/34] target/ppc: use int128.h methods in vsubcuq |
Date: |
Wed, 6 Jul 2022 17:09:30 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
And also move the insn to decodetree and remove the now unused
avr_qw_not, avr_qw_cmpu, and avr_qw_add methods.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: VĂctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220606150037.338931-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 51 +++--------------------------
target/ppc/translate/vmx-impl.c.inc | 5 +--
target/ppc/translate/vmx-ops.c.inc | 2 +-
5 files changed, 9 insertions(+), 52 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 04ced6ef70..84a41d85b0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -211,7 +211,7 @@ DEF_HELPER_FLAGS_3(VADDCUQ, TCG_CALL_NO_RWG, void, avr,
avr, avr)
DEF_HELPER_FLAGS_3(VSUBUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_4(VSUBECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(VSUBEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vsubcuq, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VSUBCUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_4(vsldoi, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
DEF_HELPER_FLAGS_3(vextractub, TCG_CALL_NO_RWG, void, avr, avr, i32)
DEF_HELPER_FLAGS_3(vextractuh, TCG_CALL_NO_RWG, void, avr, avr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5e6f3b668e..65a6a42f78 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -556,6 +556,7 @@ VADDUQM 000100 ..... ..... ..... 00100000000 @VX
VADDEUQM 000100 ..... ..... ..... ..... 111100 @VA
VADDECUQ 000100 ..... ..... ..... ..... 111101 @VA
+VSUBCUQ 000100 ..... ..... ..... 10101000000 @VX
VSUBUQM 000100 ..... ..... ..... 10100000000 @VX
VSUBECUQ 000100 ..... ..... ..... ..... 111111 @VA
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a93398fde4..d905f07d02 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2176,38 +2176,6 @@ VGENERIC_DO(popcntd, u64)
#undef VGENERIC_DO
-#ifndef CONFIG_INT128
-
-static inline void avr_qw_not(ppc_avr_t *t, ppc_avr_t a)
-{
- t->u64[0] = ~a.u64[0];
- t->u64[1] = ~a.u64[1];
-}
-
-static int avr_qw_cmpu(ppc_avr_t a, ppc_avr_t b)
-{
- if (a.VsrD(0) < b.VsrD(0)) {
- return -1;
- } else if (a.VsrD(0) > b.VsrD(0)) {
- return 1;
- } else if (a.VsrD(1) < b.VsrD(1)) {
- return -1;
- } else if (a.VsrD(1) > b.VsrD(1)) {
- return 1;
- } else {
- return 0;
- }
-}
-
-static void avr_qw_add(ppc_avr_t *t, ppc_avr_t a, ppc_avr_t b)
-{
- t->VsrD(1) = a.VsrD(1) + b.VsrD(1);
- t->VsrD(0) = a.VsrD(0) + b.VsrD(0) +
- (~a.VsrD(1) < b.VsrD(1));
-}
-
-#endif
-
void helper_VADDUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
r->s128 = int128_add(a->s128, b->s128);
@@ -2250,22 +2218,13 @@ void helper_VSUBEUQM(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b, ppc_avr_t *c)
int128_make64(int128_getlo(c->s128) & 1));
}
-void helper_vsubcuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VSUBCUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
-#ifdef CONFIG_INT128
- r->u128 = (~a->u128 < ~b->u128) ||
- (a->u128 + ~b->u128 == (__uint128_t)-1);
-#else
- int carry = (avr_qw_cmpu(*a, *b) > 0);
- if (!carry) {
- ppc_avr_t tmp;
- avr_qw_not(&tmp, *b);
- avr_qw_add(&tmp, *a, tmp);
- carry = ((tmp.VsrSD(0) == -1ull) && (tmp.VsrSD(1) == -1ull));
- }
+ Int128 tmp = int128_not(b->s128);
+
+ r->VsrD(1) = int128_ult(int128_not(a->s128), tmp) ||
+ int128_eq(int128_add(a->s128, tmp), int128_makes64(-1));
r->VsrD(0) = 0;
- r->VsrD(1) = carry;
-#endif
}
void helper_VSUBECUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 671992f7d1..e644ad3236 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1234,7 +1234,6 @@ GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
-GEN_VXFORM(vsubcuq, 0, 21);
GEN_VXFORM_TRANS(vsl, 2, 7);
GEN_VXFORM_TRANS(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
@@ -2856,9 +2855,6 @@ GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
bcdus, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
bcdtrunc, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
- bcdutrunc, PPC_NONE, PPC2_ISA300)
-
static void gen_vsbox(DisasContext *ctx)
{
@@ -3098,6 +3094,7 @@ TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper,
gen_helper_VADDUQM)
TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
+TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
diff --git a/target/ppc/translate/vmx-ops.c.inc
b/target/ppc/translate/vmx-ops.c.inc
index 9395806f3d..a3a0fd0650 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -127,7 +127,7 @@ GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC,
PPC2_ISA300),
GEN_VXFORM(vsubshs, 0, 29),
GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_300(bcdtrunc, 0, 20),
-GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_300(bcdutrunc, 0, 21),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
2.36.1
- [PULL 10/34] spapr/ddw: Reset DMA when the last non-default window is removed, (continued)
- [PULL 10/34] spapr/ddw: Reset DMA when the last non-default window is removed, Daniel Henrique Barboza, 2022/07/06
- [PULL 11/34] spapr/ddw: Implement 64bit query extension, Daniel Henrique Barboza, 2022/07/06
- [PULL 09/34] target/ppc: Change FPSCR_* to follow POWER ISA numbering convention, Daniel Henrique Barboza, 2022/07/06
- [PULL 20/34] ppc/spapr: Implement H_WATCHDOG, Daniel Henrique Barboza, 2022/07/06
- [PULL 19/34] ppc: Define SETFIELD for the ppc target, Daniel Henrique Barboza, 2022/07/06
- [PULL 16/34] target/ppc: use int128.h methods in vsubuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 14/34] target/ppc: use int128.h methods in vaddecuq and vaddeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 12/34] target/ppc: use int128.h methods in vpmsumd, Daniel Henrique Barboza, 2022/07/06
- [PULL 13/34] target/ppc: use int128.h methods in vadduqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 21/34] target/ppc: Fix insn32.decode style issues, Daniel Henrique Barboza, 2022/07/06
- [PULL 18/34] target/ppc: use int128.h methods in vsubcuq,
Daniel Henrique Barboza <=
- [PULL 17/34] target/ppc: use int128.h methods in vsubecuq and vsubeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 15/34] target/ppc: use int128.h methods in vaddcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 24/34] target/ppc: Move mffsl to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 29/34] target/ppc: implement addg6s, Daniel Henrique Barboza, 2022/07/06
- [PULL 25/34] target/ppc: Move mffs[.] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 22/34] target/ppc: Move mffscrn[i] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions, Daniel Henrique Barboza, 2022/07/06
- [PULL 27/34] tests/tcg/ppc64: Add mffsce test, Daniel Henrique Barboza, 2022/07/06
- [PULL 23/34] target/ppc: Move mffsce to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 26/34] target/ppc: Implement mffscdrn[i] instructions, Daniel Henrique Barboza, 2022/07/06