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[PULL 13/34] target/ppc: use int128.h methods in vadduqm
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 13/34] target/ppc: use int128.h methods in vadduqm |
Date: |
Wed, 6 Jul 2022 17:09:25 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: VĂctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220606150037.338931-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/int_helper.c | 8 ++------
target/ppc/translate/vmx-impl.c.inc | 3 ++-
target/ppc/translate/vmx-ops.c.inc | 1 -
5 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 39ad114c97..c6fbe4b6da 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -204,7 +204,7 @@ DEF_HELPER_FLAGS_5(vadduws, TCG_CALL_NO_RWG, void, avr,
avr, avr, avr, i32)
DEF_HELPER_FLAGS_5(vsububs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_FLAGS_5(vsubuhs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_FLAGS_5(vsubuws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
-DEF_HELPER_FLAGS_3(vadduqm, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VADDUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_4(vaddecuq, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_4(vaddeuqm, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_3(vaddcuq, TCG_CALL_NO_RWG, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0772729c6e..d6bfc2c768 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -550,6 +550,8 @@ VRLQNM 000100 ..... ..... ..... 00101000101 @VX
## Vector Integer Arithmetic Instructions
+VADDUQM 000100 ..... ..... ..... 00100000000 @VX
+
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb
VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 1476e51651..7de69f00b5 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2224,13 +2224,9 @@ static int avr_qw_addc(ppc_avr_t *t, ppc_avr_t a,
ppc_avr_t b)
#endif
-void helper_vadduqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VADDUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
-#ifdef CONFIG_INT128
- r->u128 = a->u128 + b->u128;
-#else
- avr_qw_add(r, *a, *b);
-#endif
+ r->s128 = int128_add(a->s128, b->s128);
}
void helper_vaddeuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 4c2a36405b..3fb48404d9 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1234,7 +1234,6 @@ GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
-GEN_VXFORM(vadduqm, 0, 4);
GEN_VXFORM(vaddcuq, 0, 5);
GEN_VXFORM3(vaddeuqm, 30, 0);
GEN_VXFORM3(vaddecuq, 30, 0);
@@ -3100,6 +3099,8 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
return true;
}
+TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
+
TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
diff --git a/target/ppc/translate/vmx-ops.c.inc
b/target/ppc/translate/vmx-ops.c.inc
index 26c1d957ee..065b0ba414 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -126,7 +126,6 @@ GEN_VXFORM(vsubuws, 0, 26),
GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
GEN_VXFORM(vsubshs, 0, 29),
GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_207(vadduqm, 0, 4),
GEN_VXFORM_207(vaddcuq, 0, 5),
GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
--
2.36.1
- [PULL 08/34] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 root bus, (continued)
- [PULL 08/34] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 root bus, Daniel Henrique Barboza, 2022/07/06
- [PULL 07/34] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root bus, Daniel Henrique Barboza, 2022/07/06
- [PULL 10/34] spapr/ddw: Reset DMA when the last non-default window is removed, Daniel Henrique Barboza, 2022/07/06
- [PULL 11/34] spapr/ddw: Implement 64bit query extension, Daniel Henrique Barboza, 2022/07/06
- [PULL 09/34] target/ppc: Change FPSCR_* to follow POWER ISA numbering convention, Daniel Henrique Barboza, 2022/07/06
- [PULL 20/34] ppc/spapr: Implement H_WATCHDOG, Daniel Henrique Barboza, 2022/07/06
- [PULL 19/34] ppc: Define SETFIELD for the ppc target, Daniel Henrique Barboza, 2022/07/06
- [PULL 16/34] target/ppc: use int128.h methods in vsubuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 14/34] target/ppc: use int128.h methods in vaddecuq and vaddeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 12/34] target/ppc: use int128.h methods in vpmsumd, Daniel Henrique Barboza, 2022/07/06
- [PULL 13/34] target/ppc: use int128.h methods in vadduqm,
Daniel Henrique Barboza <=
- [PULL 21/34] target/ppc: Fix insn32.decode style issues, Daniel Henrique Barboza, 2022/07/06
- [PULL 18/34] target/ppc: use int128.h methods in vsubcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 17/34] target/ppc: use int128.h methods in vsubecuq and vsubeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 15/34] target/ppc: use int128.h methods in vaddcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 24/34] target/ppc: Move mffsl to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 29/34] target/ppc: implement addg6s, Daniel Henrique Barboza, 2022/07/06
- [PULL 25/34] target/ppc: Move mffs[.] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 22/34] target/ppc: Move mffscrn[i] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions, Daniel Henrique Barboza, 2022/07/06
- [PULL 27/34] tests/tcg/ppc64: Add mffsce test, Daniel Henrique Barboza, 2022/07/06