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[PATCH v5 6/8] target/ppc: Implemented pmxvf*ger*
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From: |
Lucas Mateus Castro(alqotel) |
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Subject: |
[PATCH v5 6/8] target/ppc: Implemented pmxvf*ger* |
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Date: |
Fri, 20 May 2022 16:54:17 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update)
pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Negative accumulate
pmxvf16ger2np: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Negative multiply, Positive accumulate
pmxvf16ger2pn: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Negative accumulate
pmxvf16ger2pp: Prefixed Masked VSX Vector 16-bit Floating-Point GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvf32ger: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update)
pmxvf32gernn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf32gernp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf32gerpn: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf32gerpp: Prefixed Masked VSX Vector 32-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
pmxvf64ger: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update)
pmxvf64gernn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Negative accumulate
pmxvf64gernp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Negative multiply, Positive accumulate
pmxvf64gerpn: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Negative accumulate
pmxvf64gerpp: Prefixed Masked VSX Vector 64-bit Floating-Point GER
(rank-1 update) Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/insn64.decode | 38 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 0eed35c8cd..5ecc5c85bf 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -73,10 +73,15 @@
%xx3_xa 2:1 16:5
%xx3_xb 1:1 11:5
%xx3_at 23:3
+%xx3_xa_pair 2:1 17:4 !function=times_2
@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \
...... ... .. ..... ..... ........ ... \
&MMIRR_XX3 xa=%xx3_xa xb=%xx3_xb xt=%xx3_at
+@MMIRR_XX3_NO_P ...... .. .... .. . . ........ xmsk:4 .... \
+ ...... ... .. ..... ..... ........ ... \
+ &MMIRR_XX3 xb=%xx3_xb xt=%xx3_at pmsk=1
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -145,6 +150,39 @@ PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------
........ \
PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3
+PMXVF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00010011 ..- @MMIRR_XX3
+PMXVF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00010010 ..- @MMIRR_XX3
+PMXVF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 10010010 ..- @MMIRR_XX3
+PMXVF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 01010010 ..- @MMIRR_XX3
+PMXVF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 11010010 ..- @MMIRR_XX3
+
+PMXVF32GER 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 00011011 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERPP 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 00011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERPN 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 10011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERNP 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 01011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+PMXVF32GERNN 000001 11 1001 -- - - -------- .... ymsk:4 \
+ 111011 ... -- ..... ..... 11011010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa
+
+PMXVF64GER 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 00111011 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERPP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 00111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERPN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 10111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERNP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 01111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+PMXVF64GERNN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
+ 111011 ... -- ....0 ..... 11111010 ..- @MMIRR_XX3_NO_P
xa=%xx3_xa_pair
+
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 232a4d881e..7218394b45 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2887,6 +2887,24 @@ TRANS(XVF64GERPN, do_ger, gen_helper_XVF64GERPN)
TRANS(XVF64GERNP, do_ger, gen_helper_XVF64GERNP)
TRANS(XVF64GERNN, do_ger, gen_helper_XVF64GERNN)
+TRANS64(PMXVF16GER2, do_ger, gen_helper_XVF16GER2)
+TRANS64(PMXVF16GER2PP, do_ger, gen_helper_XVF16GER2PP)
+TRANS64(PMXVF16GER2PN, do_ger, gen_helper_XVF16GER2PN)
+TRANS64(PMXVF16GER2NP, do_ger, gen_helper_XVF16GER2NP)
+TRANS64(PMXVF16GER2NN, do_ger, gen_helper_XVF16GER2NN)
+
+TRANS64(PMXVF32GER, do_ger, gen_helper_XVF32GER)
+TRANS64(PMXVF32GERPP, do_ger, gen_helper_XVF32GERPP)
+TRANS64(PMXVF32GERPN, do_ger, gen_helper_XVF32GERPN)
+TRANS64(PMXVF32GERNP, do_ger, gen_helper_XVF32GERNP)
+TRANS64(PMXVF32GERNN, do_ger, gen_helper_XVF32GERNN)
+
+TRANS64(PMXVF64GER, do_ger, gen_helper_XVF64GER)
+TRANS64(PMXVF64GERPP, do_ger, gen_helper_XVF64GERPP)
+TRANS64(PMXVF64GERPN, do_ger, gen_helper_XVF64GERPN)
+TRANS64(PMXVF64GERNP, do_ger, gen_helper_XVF64GERNP)
+TRANS64(PMXVF64GERNN, do_ger, gen_helper_XVF64GERNN)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.31.1
- [PATCH v5 0/8] VSX MMA Implementation, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 1/8] target/ppc: Implement xxm[tf]acc and xxsetaccz, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 2/8] target/ppc: Implemented xvi*ger* instructions, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 3/8] target/ppc: Implemented pmxvi*ger* instructions, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 4/8] target/ppc: Implemented xvf*ger*, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 5/8] target/ppc: Implemented xvf16ger*, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 6/8] target/ppc: Implemented pmxvf*ger*,
Lucas Mateus Castro(alqotel) <=
- [PATCH v5 7/8] target/ppc: Implemented [pm]xvbf16ger2*, Lucas Mateus Castro(alqotel), 2022/05/20
- [PATCH v5 8/8] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap, Lucas Mateus Castro(alqotel), 2022/05/20