Re: [RFC PATCH v2 7/7] target/ppc: Implemented [pm]xvbf16ger2*

[Richard Henderson]

On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
> From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
>
> Implement the following PowerISA v3.1 instructions:
> xvbf16ger2:   VSX Vector bfloat16 GER (rank-2 update)
> xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
> Negative accumulate
> xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negative multiply,
> Positive accumulate
> xvbf16ger2pn: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
> Negative accumulate
> xvbf16ger2pp: VSX Vector bfloat16 GER (rank-2 update) Positive multiply,
> Positive accumulate
> pmxvbf16ger2:   Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
> pmxvbf16ger2nn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
> Negative multiply, Negative accumulate
> pmxvbf16ger2np: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
> Negative multiply, Positive accumulate
> pmxvbf16ger2pn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
> Positive multiply, Negative accumulate
> pmxvbf16ger2pp: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update)
> Positive multiply, Positive accumulate
>
> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
> ---
> There's a discrepancy between this implementation and mambo/the
> hardware where implementing it with float64_mul then float64r32_muladd
> sometimes results in an incorrect result after an underflow, but
> implementing with float32_mul then float32_muladd results in incorrect
> signal in some 0 or infinite results. I've not been able to solve this

I did suggest that the float64_mul needs to be done in round-to-odd.

Anyway, for this patch,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~