[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 049/101] target/ppc: Add helpers for fadds, fsubs, fdivs
From: |
Cédric Le Goater |
Subject: |
[PULL 049/101] target/ppc: Add helpers for fadds, fsubs, fdivs |
Date: |
Thu, 16 Dec 2021 21:25:22 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 3 +++
target/ppc/fpu_helper.c | 40 ++++++++++++++++++++++++++++++
target/ppc/translate/fp-impl.c.inc | 11 +++-----
3 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9d7c9a919a98..2b80c2f22835 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -94,9 +94,12 @@ DEF_HELPER_2(frip, i64, env, i64)
DEF_HELPER_2(frim, i64, env, i64)
DEF_HELPER_3(fadd, f64, env, f64, f64)
+DEF_HELPER_3(fadds, f64, env, f64, f64)
DEF_HELPER_3(fsub, f64, env, f64, f64)
+DEF_HELPER_3(fsubs, f64, env, f64, f64)
DEF_HELPER_3(fmul, f64, env, f64, f64)
DEF_HELPER_3(fdiv, f64, env, f64, f64)
+DEF_HELPER_3(fdivs, f64, env, f64, f64)
DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 07e1695b07b7..c36cf05d8098 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -521,6 +521,18 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1,
float64 arg2)
return ret;
}
+/* fadds - fadds. */
+float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_add(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
/* fsub - fsub. */
float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
{
@@ -534,6 +546,18 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1,
float64 arg2)
return ret;
}
+/* fsubs - fsubs. */
+float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_sub(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
static void float_invalid_op_mul(CPUPPCState *env, int flags,
bool set_fprc, uintptr_t retaddr)
{
@@ -585,6 +609,22 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1,
float64 arg2)
return ret;
}
+/* fdivs - fdivs. */
+float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_div(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_div(env, flags, 1, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ float_zero_divide_excp(env, GETPC());
+ }
+
+ return ret;
+}
+
static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
uint64_t ret, uint64_t ret_nan,
bool set_fprc, uintptr_t retaddr)
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index baa31d3431c7..b84097544f62 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -68,7 +68,7 @@ static void gen_f##name(DisasContext *ctx)
\
_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \
_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type);
-#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+#define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
@@ -84,10 +84,7 @@ static void gen_f##name(DisasContext *ctx)
\
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \
- gen_helper_f##op(t2, cpu_env, t0, t1); \
- if (isfloat) { \
- gen_helper_frsp(t2, cpu_env, t2); \
- } \
+ gen_helper_f##name(t2, cpu_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
@@ -100,8 +97,8 @@ static void gen_f##name(DisasContext *ctx)
\
tcg_temp_free_i64(t2); \
}
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
-_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
+_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
--
2.31.1
- [PULL 022/101] softfloat: Add flag specific to Inf * 0, (continued)
- [PULL 022/101] softfloat: Add flag specific to Inf * 0, Cédric Le Goater, 2021/12/16
- [PULL 021/101] softfloat: Add flag specific to Inf - Inf, Cédric Le Goater, 2021/12/16
- [PULL 035/101] target/ppc: Tidy inexact handling in do_fri, Cédric Le Goater, 2021/12/16
- [PULL 029/101] target/ppc: Update float_invalid_op_div for new flags, Cédric Le Goater, 2021/12/16
- [PULL 013/101] ppc/pnv.c: add a friendly warning when accel=kvm is used, Cédric Le Goater, 2021/12/16
- [PULL 024/101] softfloat: Add flag specific to sqrt(-x), Cédric Le Goater, 2021/12/16
- [PULL 037/101] target/ppc: Update fmadd for new flags, Cédric Le Goater, 2021/12/16
- [PULL 033/101] target/ppc: Remove inline from do_fri, Cédric Le Goater, 2021/12/16
- [PULL 030/101] target/ppc: Move float_check_status from FPU_FCTI to translate, Cédric Le Goater, 2021/12/16
- [PULL 042/101] target/ppc: Use helper_todouble in do_frsp, Cédric Le Goater, 2021/12/16
- [PULL 049/101] target/ppc: Add helpers for fadds, fsubs, fdivs,
Cédric Le Goater <=
- [PULL 048/101] target/ppc: Add helper for fsqrts, Cédric Le Goater, 2021/12/16
- [PULL 043/101] target/ppc: Update sqrt for new flags, Cédric Le Goater, 2021/12/16
- [PULL 056/101] target/ppc: Remove the software TLB model of 7450 CPUs, Cédric Le Goater, 2021/12/16
- [PULL 036/101] target/ppc: Clean up do_fri, Cédric Le Goater, 2021/12/16
- [PULL 040/101] target/ppc: Split out do_frsp, Cédric Le Goater, 2021/12/16
- [PULL 051/101] target/ppc: Add helper for frsqrtes, Cédric Le Goater, 2021/12/16
- [PULL 038/101] target/ppc: Split out do_fmadd, Cédric Le Goater, 2021/12/16
- [PULL 046/101] softfloat: Add float64r32 arithmetic routines, Cédric Le Goater, 2021/12/16
- [PULL 052/101] target/ppc: Update fres to new flags and float64r32, Cédric Le Goater, 2021/12/16
- [PULL 060/101] target/ppc: remove 401/403 CPUs, Cédric Le Goater, 2021/12/16