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[PULL 054/102] target/ppc: Disable software TLB for the 7450 family
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From: |
Cédric Le Goater |
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Subject: |
[PULL 054/102] target/ppc: Disable software TLB for the 7450 family |
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Date: |
Wed, 15 Dec 2021 18:03:09 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
3.15. With no known support in firmware or OS, this means that no code
for any of the 7450 CPUs is ever ran in QEMU.
Since the implementation in QEMU of the 7400 MMU is the same as the
7450, except for the software TLB vs. hardware TLB search, this patch
changes all 7450 cpus to the 7400 MMU model. This has the practical
effect of disabling the software TLB feature while keeping other
aspects of address translation working as expected.
This allow us to run software on the 7450 family again.
*- note that the 7448 is currently aliased in QEMU for a 7400, so it
is unaffected by this change.
1- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6695985e9b56..509df35d0907 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5932,7 +5932,6 @@ static void init_proc_7440(CPUPPCState *env)
0x00000000);
/* Memory management */
register_low_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5956,7 +5955,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -5976,7 +5975,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6067,7 +6066,6 @@ static void init_proc_7450(CPUPPCState *env)
0x00000000);
/* Memory management */
register_low_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6091,7 +6089,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6111,7 +6109,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6205,7 +6203,6 @@ static void init_proc_7445(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6229,7 +6226,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6249,7 +6246,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6345,7 +6342,6 @@ static void init_proc_7455(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6369,7 +6365,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6389,7 +6385,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6509,7 +6505,6 @@ static void init_proc_7457(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6533,7 +6528,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6553,7 +6548,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
--
2.31.1
- [PULL 038/102] target/ppc: Split out do_fmadd, (continued)
- [PULL 038/102] target/ppc: Split out do_fmadd, Cédric Le Goater, 2021/12/15
- [PULL 050/102] target/ppc: Add helper for fmuls, Cédric Le Goater, 2021/12/15
- [PULL 048/102] target/ppc: Add helper for fsqrts, Cédric Le Goater, 2021/12/15
- [PULL 047/102] target/ppc: Add helpers for fmadds et al, Cédric Le Goater, 2021/12/15
- [PULL 033/102] target/ppc: Remove inline from do_fri, Cédric Le Goater, 2021/12/15
- [PULL 053/102] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp, Cédric Le Goater, 2021/12/15
- [PULL 052/102] target/ppc: Update fres to new flags and float64r32, Cédric Le Goater, 2021/12/15
- [PULL 051/102] target/ppc: Add helper for frsqrtes, Cédric Le Goater, 2021/12/15
- [PULL 042/102] target/ppc: Use helper_todouble in do_frsp, Cédric Le Goater, 2021/12/15
- [PULL 049/102] target/ppc: Add helpers for fadds, fsubs, fdivs, Cédric Le Goater, 2021/12/15
- [PULL 054/102] target/ppc: Disable software TLB for the 7450 family,
Cédric Le Goater <=
- [PULL 060/102] target/ppc: remove 401/403 CPUs, Cédric Le Goater, 2021/12/15
- [PULL 055/102] target/ppc: Disable unused facilities in the e600 CPU, Cédric Le Goater, 2021/12/15
- [PULL 046/102] softfloat: Add float64r32 arithmetic routines, Cédric Le Goater, 2021/12/15
- [PULL 062/102] ppc: Mark the 'taihu' machine as deprecated, Cédric Le Goater, 2021/12/15
- [PULL 066/102] ppc/ppc405: Change ppc405ep_init() return value, Cédric Le Goater, 2021/12/15
- [PULL 058/102] target/ppc: Remove 603e exception model, Cédric Le Goater, 2021/12/15
- [PULL 056/102] target/ppc: Remove the software TLB model of 7450 CPUs, Cédric Le Goater, 2021/12/15
- [PULL 063/102] ppc: Add trace-events for DCR accesses, Cédric Le Goater, 2021/12/15
- [PULL 064/102] ppc/ppc405: Convert printfs to trace-events, Cédric Le Goater, 2021/12/15
- [PULL 043/102] target/ppc: Update sqrt for new flags, Cédric Le Goater, 2021/12/15