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[PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using
From: |
matheus . ferst |
Subject: |
[PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns |
Date: |
Fri, 29 Oct 2021 17:24:06 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsw: Vector Insert Word from GPR using immediate-specified index
vinsd: Vector Insert Doubleword from GPR using immediate-specified
index
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- #ifdef TARGET_PPC64 removed from translation code
- Comments about real hardware behavior
---
target/ppc/insn32.decode | 6 +++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b794424496..e1f76aac34 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -44,6 +44,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+&VX_uim4 vrt uim vrb
+@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -353,5 +356,8 @@ VINSWRX 000100 ..... ..... ..... 01110001111 @VX
VINSDLX 000100 ..... ..... ..... 01011001111 @VX
VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
+VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 21af60c616..9642cfa037 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1278,6 +1278,40 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a,
int size, bool right,
return ok;
}
+static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ /*
+ * PowerISA v3.1 says that the resulting value is undefined in this
+ * case, so just log a guest error and leave VRT unchanged. The
+ * real hardware would do a partial insert, e.g. if VRT is zeroed and
+ * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
+ * VRT = 0x0000...00001234, but we don't bother to reproduce this
+ * behavior as software shouldn't rely on it.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
+ gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1288,6 +1322,9 @@ TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.25.1
- [PATCH v2 09/34] target/ppc: Implement pdepd instruction, (continued)
- [PATCH v2 09/34] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 10/34] target/ppc: Implement pextd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/29
- [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions, matheus . ferst, 2021/10/29
- [PATCH v2 13/34] target/ppc: Implement vpdepd/vpextd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 14/34] target/ppc: Implement vsldbi/vsrdbi instructions, matheus . ferst, 2021/10/29
- [PATCH v2 15/34] target/ppc: Implement Vector Insert from GPR using GPR index insns, matheus . ferst, 2021/10/29
- [PATCH v2 16/34] target/ppc: Implement Vector Insert Word from GPR using Immediate insns,
matheus . ferst <=
- [PATCH v2 17/34] target/ppc: Implement Vector Insert from VSR using GPR index insns, matheus . ferst, 2021/10/29
- [PATCH v2 18/34] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 19/34] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, matheus . ferst, 2021/10/29
- [PATCH v2 20/34] target/ppc: Introduce REQUIRE_VSX macro, matheus . ferst, 2021/10/29
- [PATCH v2 21/34] target/ppc: receive high/low as argument in get/set_cpu_vsr, matheus . ferst, 2021/10/29
- [PATCH v2 22/34] target/ppc: moved stxv and lxv from legacy to decodtree, matheus . ferst, 2021/10/29