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[PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Im
From: |
matheus . ferst |
Subject: |
[PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns |
Date: |
Thu, 21 Oct 2021 16:45:30 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsw: Vector Insert Word from GPR using immediate-specified index
vinsd: Vector Insert Doubleword from GPR using immediate-specified
index
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 6 +++++
target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b794424496..e1f76aac34 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -44,6 +44,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+&VX_uim4 vrt uim vrb
+@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -353,5 +356,8 @@ VINSWRX 000100 ..... ..... ..... 01110001111 @VX
VINSDLX 000100 ..... ..... ..... 01011001111 @VX
VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
+VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 0c5f0dcf32..3b526977e4 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1283,6 +1283,37 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a,
int size, bool right,
#endif
}
+static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+#if defined(TARGET_PPC64)
+ return do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim),
+ cpu_gpr[a->vrb], gen_helper);
+#else
+ bool ok;
+ TCGv_i64 val;
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
+ gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+#endif
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1293,6 +1324,9 @@ TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.25.1
[PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns,
matheus . ferst <=
[PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns, matheus . ferst, 2021/10/21
[PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, matheus . ferst, 2021/10/21