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[PATCH 10/33] target/ppc: Implement pextd instruction
From: |
matheus . ferst |
Subject: |
[PATCH 10/33] target/ppc: Implement pextd instruction |
Date: |
Thu, 21 Oct 2021 16:45:24 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 18 ++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4a87e1258b..3c4a01fd65 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(CNTLZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(CNTTZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ff70b3e863..65075f0d03 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -206,6 +206,7 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
+PEXTD 011111 ..... ..... ..... 0010111100 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ba8ff1a475..8994e68068 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -438,6 +438,24 @@ uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
return result;
}
+uint64_t helper_PEXTD(uint64_t src, uint64_t mask)
+{
+ int i, o;
+ uint64_t result = 0;
+
+ if (mask == -1) {
+ return src;
+ }
+
+ for (o = 0; mask != 0; o++) {
+ i = ctz64(mask);
+ mask &= mask - 1;
+ result |= ((src >> i) & 1) << o;
+ }
+
+ return result;
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index c86b4621b8..37806396f2 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -451,3 +451,15 @@ static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
- Re: [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree, (continued)
- [PATCH 06/33] target/ppc: Implement PLQ and PSTQ, matheus . ferst, 2021/10/21
- [PATCH 07/33] target/ppc: Implement cntlzdm, matheus . ferst, 2021/10/21
- [PATCH 08/33] target/ppc: Implement cnttzdm, matheus . ferst, 2021/10/21
- [PATCH 09/33] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/21
- [PATCH 10/33] target/ppc: Implement pextd instruction,
matheus . ferst <=
- [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/21
- [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions, matheus . ferst, 2021/10/21
- [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction, matheus . ferst, 2021/10/21
- [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions, matheus . ferst, 2021/10/21
- [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns, matheus . ferst, 2021/10/21