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[PULL 21/25] target/ppc: add MMCR0 PMCC bits to hflags
From: |
David Gibson |
Subject: |
[PULL 21/25] target/ppc: add MMCR0 PMCC bits to hflags |
Date: |
Thu, 21 Oct 2021 15:20:23 +1100 |
From: Daniel Henrique Barboza <danielhb413@gmail.com>
We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1. This requires several PMU related
registers to be exposed to userspace (problem state). PowerISA v3.1
dictates that the PMCC bits of the MMCR0 register controls the level of
access of the PMU registers to problem state.
This patch start things off by exposing both PMCC bits to hflags,
allowing us to access them via DisasContext in the read/write callbacks
that we're going to add next.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 6 ++++++
target/ppc/helper_regs.c | 6 ++++++
target/ppc/translate.c | 4 ++++
3 files changed, 16 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cc1911bc75..24d1f2cf97 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -343,6 +343,10 @@ typedef struct ppc_v3_pate_t {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+/* PMU bits */
+#define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
+#define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
@@ -608,6 +612,8 @@ enum {
HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
HFLAGS_FP = 13, /* MSR_FP */
HFLAGS_PR = 14, /* MSR_PR */
+ HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
+ HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 1bfb480ecf..99562edd57 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -109,6 +109,12 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
if (env->spr[SPR_LPCR] & LPCR_HR) {
hflags |= 1 << HFLAGS_HR;
}
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) {
+ hflags |= 1 << HFLAGS_PMCC0;
+ }
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
+ hflags |= 1 << HFLAGS_PMCC1;
+ }
#ifndef CONFIG_USER_ONLY
if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d0d400cd8c..a4c5ef3701 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -175,6 +175,8 @@ struct DisasContext {
bool tm_enabled;
bool gtse;
bool hr;
+ bool mmcr0_pmcc0;
+ bool mmcr0_pmcc1;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint32_t flags;
@@ -8552,6 +8554,8 @@ static void ppc_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
ctx->hr = (hflags >> HFLAGS_HR) & 1;
+ ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
+ ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
ctx->singlestep_enabled = 0;
if ((hflags >> HFLAGS_SE) & 1) {
--
2.31.1
- [PULL 09/25] linux-user/ppc: Fix XER access in save/restore_user_regs, (continued)
- [PULL 09/25] linux-user/ppc: Fix XER access in save/restore_user_regs, David Gibson, 2021/10/21
- [PULL 14/25] ppc/pegasos2: Warn when using VOF but no kernel is specified, David Gibson, 2021/10/21
- [PULL 15/25] ppc/pegasos2: Implement get-time-of-day RTAS function with VOF, David Gibson, 2021/10/21
- [PULL 20/25] target/ppc: Filter mtmsr[d] input before setting MSR, David Gibson, 2021/10/21
- [PULL 13/25] ppc/pegasos2: Restrict memory to 2 gigabytes, David Gibson, 2021/10/21
- [PULL 17/25] ppc/pegasos2: Add constants for PCI config addresses, David Gibson, 2021/10/21
- [PULL 16/25] ppc/pegasos2: Access MV64361 registers via their memory region, David Gibson, 2021/10/21
- [PULL 22/25] target/ppc: add user read/write functions for MMCR0, David Gibson, 2021/10/21
- [PULL 06/25] spapr/xive: Use xive_esb_rw() to trigger interrupts, David Gibson, 2021/10/21
- [PULL 08/25] tests/acceptance: Add tests for the ppc405 boards, David Gibson, 2021/10/21
- [PULL 21/25] target/ppc: add MMCR0 PMCC bits to hflags,
David Gibson <=
- [PULL 25/25] hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels, David Gibson, 2021/10/21
- [PULL 23/25] target/ppc: add user read/write functions for MMCR2, David Gibson, 2021/10/21
- [PULL 24/25] target/ppc: adding user read/write functions for PMCs, David Gibson, 2021/10/21
- Re: [PULL 00/25] ppc-for-6.2 queue 20211021, Richard Henderson, 2021/10/21