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Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction
From: |
David Gibson |
Subject: |
Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction |
Date: |
Mon, 18 Oct 2021 14:13:09 +1100 |
On Sun, Oct 17, 2021 at 10:01:18PM -0300, Daniel Henrique Barboza wrote:
> This new version presents drastic design changes across all areas, most
> of them based on the feedback received in v3.
>
> - TCG reviewers: for people looking to review only TCG related changes,
> here's a summmary of where are the TCG code in the series:
>
> * Patches that have a lot of TCG/translation changes: 1-4, 9, 13
> * Patches that have TCG/translation bits: 6, 7, 10, 11
Patches 1..4 applied to ppc-for-6.2, still looking at the rest.
> - changes in v3:
>
> The most drastic change is in the PMU. We're now working with an
> abstraction called PMUEvent that holds all the event information that
> the helper functions need to process it: the PMC, the event type and an
> overflow timer for cycle events. The PMU will always have 6 PMCEvent
> structs, one for each counter. Counters that aren't being used in that
> moment will have event type 'invalid'. These events are populated only
> when MMCR1 is written. Calculating the PMC values does not require
> multiple calls to 'get_PMC_event()', which has been deleted. In fact,
> this design change cut 60 lines of the power8-pmu.c file compared to the
> previous version, resulting in a more concise logic that will allow for
> easier extension of the PMU in the future.
>
> Another change was related to PMCC bits and access control of problem
> state to PMU registers. We're now exposing both PMCC bits and doing a
> proper access control for groupA regs.
>
> A new file was created to host the PMU translation code. The 300+ lines
> of the new power8-pmu-regs.c.inc file would be dumped into translate.c.
>
> I've also changed the patch order. The exclusive EBB patches were pushed to
> the end of the series. I find it easier to add the placeholders for the
> PMC interrupt right at the start but populate them later on, after all
> the PMU logic has already been in place, instead of adding PMU code,
> then EBB, then go back to PMU code again.
>
> All other changes were result of these decisions described above.
>
> - patch 13 (former 08):
> * renamed arg_RFEBB to arg_XL_s
> * added Matheus' R-b
> - other patches:
> * The changes were so substancial that the patch breakdown with the diffs
> turned out cumbersome and contraproductive.
> - v3 link:
> https://lists.gnu.org/archive/html/qemu-devel/2021-09/msg01250.html
>
>
> Daniel Henrique Barboza (13):
> target/ppc: add MMCR0 PMCC bits to hflags
> target/ppc: add user read/write functions for MMCR2
> target/ppc: adding user read/write functions for PMCs
> target/ppc: introduce PMU events
> target/ppc: initialize PMUEvents on MMCR1 write
> target/ppc: PMU basic cycle count for pseries TCG
> target/ppc: enable PMU counter overflow with cycle events
> target/ppc: enable PMU instruction count
> target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
> target/ppc: PMU: handle setting of PMCs while running
> target/ppc/power8-pmu.c: handle overflow bits when PMU is running
> PPC64/TCG: Implement 'rfebb' instruction
> target/ppc/excp_helper.c: EBB handling adjustments
>
> Gustavo Romero (2):
> target/ppc: add user read/write functions for MMCR0
> target/ppc: PMU Event-Based exception support
>
> hw/ppc/spapr_cpu_core.c | 6 +
> target/ppc/cpu.h | 89 +++++-
> target/ppc/cpu_init.c | 38 +--
> target/ppc/excp_helper.c | 92 ++++++
> target/ppc/helper.h | 5 +
> target/ppc/helper_regs.c | 10 +
> target/ppc/insn32.decode | 5 +
> target/ppc/meson.build | 1 +
> target/ppc/power8-pmu-regs.c.inc | 320 +++++++++++++++++++
> target/ppc/power8-pmu.c | 410 +++++++++++++++++++++++++
> target/ppc/power8-pmu.h | 25 ++
> target/ppc/spr_tcg.h | 12 +
> target/ppc/translate.c | 67 ++++
> target/ppc/translate/branch-impl.c.inc | 33 ++
> 14 files changed, 1093 insertions(+), 20 deletions(-)
> create mode 100644 target/ppc/power8-pmu-regs.c.inc
> create mode 100644 target/ppc/power8-pmu.c
> create mode 100644 target/ppc/power8-pmu.h
> create mode 100644 target/ppc/translate/branch-impl.c.inc
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v4 05/15] target/ppc: introduce PMU events, (continued)
- [PATCH v4 05/15] target/ppc: introduce PMU events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 14/15] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 09/15] target/ppc: enable PMU instruction count, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction,
David Gibson <=