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[PATCH v4 09/15] target/ppc: enable PMU instruction count
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 09/15] target/ppc: enable PMU instruction count |
Date: |
Sun, 17 Oct 2021 22:01:27 -0300 |
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions
(Perf event PM_INST_CMPL) by counting the amount of instructions
translated in each translation block right before exiting it.
A new pmu_count_insns() helper in translation.c was added to do that.
After verifying that the PMU is running (MMCR0_FC bit not set), call
helper_insns_inc(). This new helper from power8-pmu.c will add the
instructions to the relevant counters. It'll also be responsible for
triggering counter negative overflows as it is already being done with
cycles.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 1 +
target/ppc/helper.h | 1 +
target/ppc/helper_regs.c | 4 +++
target/ppc/power8-pmu-regs.c.inc | 6 ++++
target/ppc/power8-pmu.c | 41 ++++++++++++++++++++++++++++
target/ppc/translate.c | 47 ++++++++++++++++++++++++++++++++
6 files changed, 100 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 074d844741..185a6166aa 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -665,6 +665,7 @@ enum {
HFLAGS_PR = 14, /* MSR_PR */
HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
+ HFLAGS_MMCR0FC = 17, /* MMCR0 FC bit */
HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea82d08ad5..5814e2f251 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -22,6 +22,7 @@ DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
DEF_HELPER_2(store_mmcr1, void, env, tl)
+DEF_HELPER_2(insns_inc, void, env, i32)
#endif
DEF_HELPER_1(check_tlb_flush_local, void, env)
DEF_HELPER_1(check_tlb_flush_global, void, env)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 99562edd57..875c2fdfc6 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -115,6 +115,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
hflags |= 1 << HFLAGS_PMCC1;
}
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
+ hflags |= 1 << HFLAGS_MMCR0FC;
+ }
+
#ifndef CONFIG_USER_ONLY
if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 8b3ffd9c1a..f8ca44cfdc 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -113,6 +113,12 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val)
*/
gen_icount_io_start(ctx);
gen_helper_store_mmcr0(cpu_env, val);
+
+ /*
+ * End the translation block because MMCR0 writes can change
+ * ctx->pmu_frozen.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 724a1a4038..e9c6b9dfec 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -102,6 +102,33 @@ static bool pmu_event_has_overflow_enabled(CPUPPCState
*env, PMUEvent *event)
return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
}
+static bool pmu_events_increment_insns(CPUPPCState *env, uint32_t num_insns)
+{
+ bool overflow_triggered = false;
+ int i;
+
+ /* PMC6 never counts instructions. */
+ for (i = 0; i < PMU_EVENTS_NUM - 1; i++) {
+ PMUEvent *event = &env->pmu_events[i];
+
+ if (!pmu_event_is_active(env, event) ||
+ event->type != PMU_EVENT_INSTRUCTIONS) {
+ continue;
+ }
+
+ env->spr[event->sprn] += num_insns;
+
+ if (env->spr[event->sprn] >= COUNTER_NEGATIVE_VAL &&
+ pmu_event_has_overflow_enabled(env, event)) {
+
+ overflow_triggered = true;
+ env->spr[event->sprn] = COUNTER_NEGATIVE_VAL;
+ }
+ }
+
+ return overflow_triggered;
+}
+
static void pmu_events_update_cycles(CPUPPCState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -248,6 +275,20 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
return;
}
+/* This helper assumes that the PMC is running. */
+void helper_insns_inc(CPUPPCState *env, uint32_t num_insns)
+{
+ bool overflow_triggered;
+ PowerPCCPU *cpu;
+
+ overflow_triggered = pmu_events_increment_insns(env, num_insns);
+
+ if (overflow_triggered) {
+ cpu = env_archcpu(env);
+ fire_PMC_interrupt(cpu);
+ }
+}
+
static void cpu_ppc_pmu_timer_cb(void *opaque)
{
PowerPCCPU *cpu = opaque;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 96e8703dd1..acc0e50194 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -178,6 +178,7 @@ struct DisasContext {
bool hr;
bool mmcr0_pmcc0;
bool mmcr0_pmcc1;
+ bool pmu_frozen;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint32_t flags;
@@ -4304,6 +4305,31 @@ static inline void gen_update_cfar(DisasContext *ctx,
target_ulong nip)
#endif
}
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void pmu_count_insns(DisasContext *ctx)
+{
+ /* Do not bother calling the helper if the PMU is frozen */
+ if (ctx->pmu_frozen) {
+ return;
+ }
+
+ /*
+ * The PMU insns_inc() helper stops the internal PMU timer if a
+ * counter overflows happens. In that case, if the guest is
+ * running with icount and we do not handle it beforehand,
+ * the helper can trigger a 'bad icount read'.
+ */
+ gen_icount_io_start(ctx);
+
+ gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
+}
+#else
+static void pmu_count_insns(DisasContext *ctx)
+{
+ return;
+}
+#endif
+
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
return translator_use_goto_tb(&ctx->base, dest);
@@ -4318,9 +4344,18 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
} else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
gen_helper_raise_exception(cpu_env,
tcg_constant_i32(gen_prep_dbgex(ctx)));
} else {
+ pmu_count_insns(ctx);
tcg_gen_exit_tb(NULL, 0);
}
} else {
+ /*
+ * tcg_gen_lookup_and_goto_ptr will exit the TB if
+ * CF_NO_GOTO_PTR is set. Count insns now.
+ */
+ if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
+ pmu_count_insns(ctx);
+ }
+
tcg_gen_lookup_and_goto_ptr();
}
}
@@ -4332,6 +4367,7 @@ static void gen_goto_tb(DisasContext *ctx, int n,
target_ulong dest)
dest = (uint32_t) dest;
}
if (use_goto_tb(ctx, dest)) {
+ pmu_count_insns(ctx);
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_nip, dest & ~3);
tcg_gen_exit_tb(ctx->base.tb, n);
@@ -8565,6 +8601,7 @@ static void ppc_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->hr = (hflags >> HFLAGS_HR) & 1;
ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
+ ctx->pmu_frozen = (hflags >> HFLAGS_MMCR0FC) & 1;
ctx->singlestep_enabled = 0;
if ((hflags >> HFLAGS_SE) & 1) {
@@ -8685,6 +8722,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
switch (is_jmp) {
case DISAS_TOO_MANY:
if (use_goto_tb(ctx, nip)) {
+ pmu_count_insns(ctx);
tcg_gen_goto_tb(0);
gen_update_nip(ctx, nip);
tcg_gen_exit_tb(ctx->base.tb, 0);
@@ -8695,6 +8733,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
gen_update_nip(ctx, nip);
/* fall through */
case DISAS_CHAIN:
+ /*
+ * tcg_gen_lookup_and_goto_ptr will exit the TB if
+ * CF_NO_GOTO_PTR is set. Count insns now.
+ */
+ if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
+ pmu_count_insns(ctx);
+ }
+
tcg_gen_lookup_and_goto_ptr();
break;
@@ -8702,6 +8748,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
gen_update_nip(ctx, nip);
/* fall through */
case DISAS_EXIT:
+ pmu_count_insns(ctx);
tcg_gen_exit_tb(NULL, 0);
break;
--
2.31.1
- [PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags, (continued)
- [PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 04/15] target/ppc: adding user read/write functions for PMCs, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 03/15] target/ppc: add user read/write functions for MMCR2, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 02/15] target/ppc: add user read/write functions for MMCR0, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 06/15] target/ppc: initialize PMUEvents on MMCR1 write, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 05/15] target/ppc: introduce PMU events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 14/15] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 09/15] target/ppc: enable PMU instruction count,
Daniel Henrique Barboza <=
- [PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction, David Gibson, 2021/10/17