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[PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle even
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events |
Date: |
Sun, 17 Oct 2021 22:01:26 -0300 |
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.
For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer of the PMUEvent to expire in the moment the overflow
would be occuring. The timer will call fire_PMC_interrupt() (via
cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the
conditions are met, an EBB exception.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/power8-pmu.c | 75 +++++++++++++++++++++++++++++++++++++++--
2 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e6bb55cb1a..074d844741 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -373,6 +373,8 @@ typedef struct PMUEvent {
#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
+#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
+#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 55906c70a2..724a1a4038 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -23,6 +23,8 @@
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+#define COUNTER_NEGATIVE_VAL 0x80000000
+
/*
* For PMCs 1-4, IBM POWER chips has support for an implementation
* dependent event, 0x1E, that enables cycle counting. The Linux kernel
@@ -91,6 +93,15 @@ static bool pmu_event_is_active(CPUPPCState *env, PMUEvent
*event)
return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56);
}
+static bool pmu_event_has_overflow_enabled(CPUPPCState *env, PMUEvent *event)
+{
+ if (event->sprn == SPR_POWER_PMC1) {
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE;
+ }
+
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
+}
+
static void pmu_events_update_cycles(CPUPPCState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -121,6 +132,52 @@ static void pmu_events_update_cycles(CPUPPCState *env)
}
}
+static void pmu_delete_timers(CPUPPCState *env)
+{
+ int i;
+
+ for (i = 0; i < PMU_EVENTS_NUM; i++) {
+ PMUEvent *event = &env->pmu_events[i];
+
+ if (event->sprn == SPR_POWER_PMC5) {
+ continue;
+ }
+
+ timer_del(event->cyc_overflow_timer);
+ }
+}
+
+static void pmu_events_start_overflow_timers(CPUPPCState *env)
+{
+ uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ int64_t timeout;
+ int i;
+
+ env->pmu_base_time = now;
+
+ /*
+ * Scroll through all PMCs ad start counter overflow timers for
+ * PM_CYC events, if needed.
+ */
+ for (i = 0; i < PMU_EVENTS_NUM; i++) {
+ PMUEvent *event = &env->pmu_events[i];
+
+ if (!pmu_event_is_active(env, event) ||
+ !(event->type == PMU_EVENT_CYCLES) ||
+ !pmu_event_has_overflow_enabled(env, event)) {
+ continue;
+ }
+
+ if (env->spr[event->sprn] >= COUNTER_NEGATIVE_VAL) {
+ timeout = 0;
+ } else {
+ timeout = COUNTER_NEGATIVE_VAL - env->spr[event->sprn];
+ }
+
+ timer_mod(event->cyc_overflow_timer, now + timeout);
+ }
+}
+
/*
* A cycle count session consists of the basic operations we
* need to do to support PM_CYC events: redefine a new base_time
@@ -128,8 +185,22 @@ static void pmu_events_update_cycles(CPUPPCState *env)
*/
static void start_cycle_count_session(CPUPPCState *env)
{
- /* Just define pmu_base_time for now */
- env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ bool overflow_enabled = env->spr[SPR_POWER_MMCR0] &
+ (MMCR0_PMC1CE | MMCR0_PMCjCE);
+
+ /*
+ * Always delete existing overflow timers when starting a
+ * new cycle counting session.
+ */
+ pmu_delete_timers(env);
+
+ if (!overflow_enabled) {
+ /* Define pmu_base_time and leave */
+ env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ return;
+ }
+
+ pmu_events_start_overflow_timers(env);
}
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
--
2.31.1
- [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 04/15] target/ppc: adding user read/write functions for PMCs, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 03/15] target/ppc: add user read/write functions for MMCR2, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 02/15] target/ppc: add user read/write functions for MMCR0, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 06/15] target/ppc: initialize PMUEvents on MMCR1 write, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 05/15] target/ppc: introduce PMU events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events,
Daniel Henrique Barboza <=
- [PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 14/15] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 09/15] target/ppc: enable PMU instruction count, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction, David Gibson, 2021/10/17