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[PULL 01/18] xive: Remove extra '0x' prefix in trace events
From: |
David Gibson |
Subject: |
[PULL 01/18] xive: Remove extra '0x' prefix in trace events |
Date: |
Fri, 27 Aug 2021 17:09:29 +1000 |
From: Cédric Le Goater <clg@kaod.org>
Cc: thuth@redhat.com
Fixes: 4e960974d4ee ("xive: Add trace events")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/519
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809085227.288523-1-clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/trace-events | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index e56e7dd3b6..6a17d38998 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -219,14 +219,14 @@ kvm_xive_source_reset(uint32_t srcno) "IRQ 0x%x"
xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr,
uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x
CPPR=0x%02x NSR=0x%02x ACK"
xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr,
uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x
CPPR=0x%02x NSR=0x%02x raise !"
xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr,
uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x new
CPPR=0x%02x NSR=0x%02x"
-xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value)
"@0x0x%"PRIx64" IRQ 0x%x val=0x0x%"PRIx64
-xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value)
"@0x0x%"PRIx64" IRQ 0x%x val=0x0x%"PRIx64
+xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value)
"@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
+xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value)
"@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data)
"END 0x%02x/0x%04x -> enqueue 0x%08x"
xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk,
uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END
0x%02x/0x%04x data 0x%08x"
-xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value)
"@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
-xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value)
"@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value)
"@0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value)
"@0x%"PRIx64" sz=%d val=0x%" PRIx64
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found
NVT 0x%x/0x%x ring=0x%x"
-xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END
0x%x/0x%x @0x0x%"PRIx64
+xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END
0x%x/0x%x @0x%"PRIx64
# pnv_xive.c
pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64"
val=0x%"PRIx64
--
2.31.1
- [PULL 00/18] ppc-for-6.2 queue 20210827, David Gibson, 2021/08/27
- [PULL 02/18] spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree, David Gibson, 2021/08/27
- [PULL 01/18] xive: Remove extra '0x' prefix in trace events,
David Gibson <=
- [PULL 04/18] target/ppc: moved ppc_store_sdr1 to mmu_common.c, David Gibson, 2021/08/27
- [PULL 03/18] target/ppc: divided mmu_helper.c in 2 files, David Gibson, 2021/08/27
- [PULL 05/18] target/ppc: moved store_40x_sler to helper_regs.c, David Gibson, 2021/08/27
- [PULL 09/18] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode, David Gibson, 2021/08/27
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, David Gibson, 2021/08/27
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, David Gibson, 2021/08/27
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines, David Gibson, 2021/08/27
- [PULL 12/18] ppc/pnv: add a chip topology index for POWER10, David Gibson, 2021/08/27
- [PULL 11/18] ppc/pnv: Distribute RAM among the chips, David Gibson, 2021/08/27