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[PATCH v2 08/16] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 08/16] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits |
Date: |
Tue, 24 Aug 2021 13:30:24 -0300 |
We're missing two counter freeze bits that are used to further control
how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen
PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes
PMCs 5 and 6.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/power8_pmu.c | 25 ++++++++++++++++++++++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 60e5e1159a..105ee75a01 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -349,6 +349,8 @@ typedef struct ppc_v3_pate_t {
#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
+#define MMCR0_FC14 PPC_BIT(58)
+#define MMCR0_FC56 PPC_BIT(59)
#define MMCR1_PMC1SEL_SHIFT (63 - 39)
#define MMCR1_PMC1SEL PPC_BITMASK(32, 39)
diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c
index 9154fca5fd..4545fe7810 100644
--- a/target/ppc/power8_pmu.c
+++ b/target/ppc/power8_pmu.c
@@ -58,6 +58,15 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn)
return event;
}
+static bool pmc_is_running(CPUPPCState *env, int sprn)
+{
+ if (sprn < SPR_POWER_PMC5) {
+ return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14);
+ }
+
+ return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56);
+}
+
static void update_programmable_PMC_reg(CPUPPCState *env, int sprn,
uint64_t time_delta)
{
@@ -90,13 +99,19 @@ static void update_cycles_PMCs(CPUPPCState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
uint64_t time_delta = now - env->pmu_base_time;
+ bool PMC14_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14);
+ bool PMC6_running = !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56);
int sprn;
- for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) {
- update_programmable_PMC_reg(env, sprn, time_delta);
+ if (PMC14_running) {
+ for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) {
+ update_programmable_PMC_reg(env, sprn, time_delta);
+ }
}
- update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta);
+ if (PMC6_running) {
+ update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta);
+ }
}
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
@@ -136,6 +151,10 @@ static bool pmc_counting_insns(CPUPPCState *env, int sprn,
{
bool ret = false;
+ if (!pmc_is_running(env, sprn)) {
+ return false;
+ }
+
if (sprn == SPR_POWER_PMC5) {
return true;
}
--
2.31.1
- [PATCH v2 04/16] target/ppc: PMU basic cycle count for pseries TCG, (continued)
- [PATCH v2 04/16] target/ppc: PMU basic cycle count for pseries TCG, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 05/16] target/ppc/power8_pmu.c: enable PMC1-PMC4 events, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 06/16] target/ppc: PMU: add instruction counting, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 07/16] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 08/16] target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits,
Daniel Henrique Barboza <=
- [PATCH v2 09/16] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 10/16] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 11/16] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 12/16] target/ppc/power8_pmu.c: enable PMC1 counter negative overflow, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 13/16] target/ppc/power8_pmu.c: cycles overflow with all PMCs, Daniel Henrique Barboza, 2021/08/24
- [PATCH v2 14/16] target/ppc: PMU: insns counter negative overflow support, Daniel Henrique Barboza, 2021/08/24