Re:e6500 stvx instruction

[mario]

If anyone is willing to give it a try, I have prepared an HDD image with Debian 10 installed using

https://cdimage.debian.org/cdimage/ports/10.0/ppc64/iso-cd/debian-10.0-ppc64-NETINST-1.iso

Mind that the HDD image is quite big, I could not end up with a smaller one, 973MB gz compressed, 992MB uncompressed

https://repo.powerprogress.org/t2080rdb/hdd_debian_sid_ppc64_basic.qcow2.gz

I also prepared a zip file with a series of kernel binaries (58MB) with:

1) kernel 5.12.10 compiled for Book3e e5500 target

2) kernel 5.12.10 compiled for Book3e e6500 target

3) kernel 5.10 provided by Debian compiled for any Book3s

4) the terminal output from qemu-system-ppc64 with a cpu e5500

5) the terminal output from qemu-system-ppc64 with a cpu e6500

6) the serial output from a NXP T2080RDB mounting a real e6500

This is the link to the file

https://repo.powerprogress.org/t2080rdb/hdd_debian_sid_ppc64_basic_kernels.zip

Here you may find the NXP manual of the e6500 CPU

https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf

For those of you that will need a real e6500 CPU I can provide remote access to an NXP T2080RDB

https://www.powerprogress.org/en/diy/t2080rdb-desktop-user-guide/

From "BALATON Zoltan" balaton@eik.bme.hu

To qemu-ppc@nongnu.org

Cc mario@locati.it

Date Tue, 15 Jun 2021 21:03:44 +0200 (CEST)

Subject e6500 stvx instruction

Hello,

 

Trying to boot an installed Debian Linux 10 with -M ppce500 -cpu e6500

fails with an assert:

 

----------------

IN:

0x3fffbe09b820: 7e8029ce stvx v20, 0, r5

 

qemu: fatal: Raised an exception without defined vector 73

 

NIP 00003fffbe09b820 LR 00003fffbe098f3c CTR 00003fffbe098ed0 XER 0000000000000000 CPU#0

MSR 000000008002f002 HID0 0000000000000000 HF 00006006 iidx 0 didx 0

TB 00000000 1559667347 DECR 289366

GPR00 0000000000000000 00003fffc2fd22a0 00003fffbe0c2e00 00003fffc2fd2320

GPR04 0000000000000000 00003fffc2fd2460 00003fffc2fd2470 7f7f7f7f7f7f7f7f

GPR08 00000001103ed290 00003fffc2fd2310 00003fffc2fd25b0 0000000000000000

GPR12 00003fffbe098ed0 0000000000000000 00003fffc2fd2660 00003fffc2fd2660

GPR16 00003fffbe0b9940 00003fffc2fd2660 4f524947494e5f50 00003fffbe0b9eb8

GPR20 00003fffc2fd2aa0 00003fffc2fd2ac8 0000000000000000 00000001103e78f8

GPR24 00000001103ed27d 0000000000000001 00003fffbe0bc1b8 0000000000000000

GPR28 00003fffc2fd2aa0 00003fffbe0b9eb8 0000000000000000 00003fffc2fd2ac8

CR 28002281 [ E L - - E E L -O ] RES ffffffffffffffff

FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000

FPSCR 0000000000000000

SRR0 00003fffbe09b6a4 SRR1 000000008002f002 PVR 0000000080400020 VRSAVE 0000000000000000

SPRG0 0000000000000000 SPRG1 c000000001b2f000 SPRG2 c000000001b2f098 SPRG3 0000000000000000

SPRG4 0000000000000000 SPRG5 0000000000000000 SPRG6 0000000000000000 SPRG7 0000000000000000

CSRR0 0000000000000000 CSRR1 0000000000000000 MCSRR0 0000000000000000 MCSRR1 0000000000000000

TCR 0000000004000000 TSR 0000000000000000 ESR 0000000000000000 DEAR 00003fffbe077d90

PIR 0000000000000000 DECAR 0000000000000000 IVPR c000000000010000 EPCR 0000000003000000

MCSR 0000000000000000 SPRG8 0000000000000000 EPR 00000000000000e0

MCAR 0000000000000000 PID1 0000000000000000 PID2 0000000000000000 SVR 0000000000000000

MAS0 0000000000050006 MAS1 0000000080010100 MAS2 00003fffbe077004 MAS3 0000000001781023

MAS4 0000000000000104 MAS6 0000000000010000 MAS7 0000000000000000 PID 0000000000000001

MMUCFG 0000000006510b45 TLB0CFG 0000000008052400 TLB1CFG 0000000040028040

Aborted (core dumped)

 

The assert is from

 

https://git.qemu.org/?p=qemu.git;a=blob;f=target/ppc/excp_helper.c;h=fd147e2a37662456d30f7ab74b23bfb036260ced;hb=HEAD#l877

 

and in cpu.h

 

POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */

 

But the e6500 supports Altivec and the appropriate flag is set in

cpu_init,c so I think this should not happen. Also the stvx is listed in

the docs for e6500 as a valid instruction as far as I can see. I've tried

searching for it in target/ppc but I did not find anything. Is stvx

implemented and if not how should it be implemented?

 

This was reported by Mario in cc and he could test patches or provide more

details I think.

 

Regards,

BALATON Zoltan