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Re: [RFC PATCH 1/5] target/ppc: powerpc_excp: Move lpes code to where it
From: |
David Gibson |
Subject: |
Re: [RFC PATCH 1/5] target/ppc: powerpc_excp: Move lpes code to where it is used |
Date: |
Wed, 2 Jun 2021 17:37:06 +1000 |
On Tue, Jun 01, 2021 at 06:46:45PM -0300, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Applied to ppc-for-6.1.
> ---
> target/ppc/excp_helper.c | 47 +++++++++++++++++++++-------------------
> 1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 04418054f5..5ea8503b46 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -333,7 +333,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> CPUPPCState *env = &cpu->env;
> target_ulong msr, new_msr, vector;
> int srr0, srr1, asrr0, asrr1, lev = -1;
> - bool lpes0;
>
> qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> " => %08x (%02x)\n", env->nip, excp, env->error_code);
> @@ -365,27 +364,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> }
>
> - /*
> - * Exception targeting modifiers
> - *
> - * LPES0 is supported on POWER7/8/9
> - * LPES1 is not supported (old iSeries mode)
> - *
> - * On anything else, we behave as if LPES0 is 1
> - * (externals don't alter MSR:HV)
> - */
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8 ||
> - excp_model == POWERPC_EXCP_POWER9 ||
> - excp_model == POWERPC_EXCP_POWER10) {
> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - } else
> -#endif /* defined(TARGET_PPC64) */
> - {
> - lpes0 = true;
> - }
> -
> /*
> * Hypervisor emulation assistance interrupt only exists on server
> * arch 2.05 server or later. We also don't want to generate it if
> @@ -473,8 +451,32 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> msr |= env->error_code;
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input
> */
> + {
> + bool lpes0;
> +
> cs = CPU(cpu);
>
> + /*
> + * Exception targeting modifiers
> + *
> + * LPES0 is supported on POWER7/8/9
> + * LPES1 is not supported (old iSeries mode)
> + *
> + * On anything else, we behave as if LPES0 is 1
> + * (externals don't alter MSR:HV)
> + */
> +#if defined(TARGET_PPC64)
> + if (excp_model == POWERPC_EXCP_POWER7 ||
> + excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9 ||
> + excp_model == POWERPC_EXCP_POWER10) {
> + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> + } else
> +#endif /* defined(TARGET_PPC64) */
> + {
> + lpes0 = true;
> + }
> +
> if (!lpes0) {
> new_msr |= (target_ulong)MSR_HVB;
> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> @@ -486,6 +488,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> }
> break;
> + }
> case POWERPC_EXCP_ALIGN: /* Alignment exception
> */
> /* Get rS/rD and rA from faulting opcode */
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [RFC PATCH 0/5] target/ppc: powerpc_excp improvements - part I, Fabiano Rosas, 2021/06/01
- [RFC PATCH 1/5] target/ppc: powerpc_excp: Move lpes code to where it is used, Fabiano Rosas, 2021/06/01
- Re: [RFC PATCH 1/5] target/ppc: powerpc_excp: Move lpes code to where it is used,
David Gibson <=
- [RFC PATCH 3/5] target/ppc: powerpc_excp: Consolidade TLB miss code, Fabiano Rosas, 2021/06/01
- [RFC PATCH 4/5] target/ppc: powerpc_excp: Standardize arguments to interrupt code, Fabiano Rosas, 2021/06/01
- [RFC PATCH 2/5] target/ppc: powerpc_excp: Remove dump_syscall_vectored, Fabiano Rosas, 2021/06/01
- [RFC PATCH 5/5] target/ppc: powerpc_excp: Move interrupt raising code to QOM, Fabiano Rosas, 2021/06/01