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Re: [Qemu-ppc] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field |
Date: |
Wed, 19 Dec 2018 17:41:35 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:39:09PM -0800, Richard Henderson wrote:
> Change the representation of VSCR_SAT such that it is easy
> to set from vector code.
>
> Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> ---
> target/ppc/cpu.h | 4 +++-
> target/ppc/int_helper.c | 11 ++++++++---
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index a2fe6058b1..26d2e16720 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1063,10 +1063,12 @@ struct CPUPPCState {
> /* Special purpose registers */
> target_ulong spr[1024];
> ppc_spr_t spr_cb[1024];
> - /* Vector status and control register */
> + /* Vector status and control register, minus VSCR_SAT. */
> uint32_t vscr;
> /* VSX registers (including FP and AVR) */
> ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
> + /* Non-zero if and only if VSCR_SAT should be set. */
> + ppc_vsr_t vscr_sat;
> /* SPE registers */
> uint64_t spe_acc;
> uint32_t spe_fscr;
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 38aa3e85a6..9dbcbcd87a 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -471,18 +471,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh)
>
> void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
> {
> - env->vscr = vscr;
> + env->vscr = vscr & ~(1u << VSCR_SAT);
> + /* Which bit we set is completely arbitrary, but clear the rest. */
> + env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
> + env->vscr_sat.u64[1] = 0;
> set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
> }
>
> uint32_t helper_mfvscr(CPUPPCState *env)
> {
> - return env->vscr;
> + uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
> + return env->vscr | (sat << VSCR_SAT);
> }
>
> static inline void set_vscr_sat(CPUPPCState *env)
> {
> - env->vscr |= 1 << VSCR_SAT;
> + /* The choice of non-zero value is arbitrary. */
> + env->vscr_sat.u32[0] = 1;
> }
>
> void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, (continued)
- [Qemu-ppc] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 31/34] target/ppc: Add set_vscr_sat, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 04/34] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field, Richard Henderson, 2018/12/18
- Re: [Qemu-ppc] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field,
David Gibson <=
- [Qemu-ppc] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 29/34] target/ppc: Add helper_mfvscr, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 10/34] target/arm: Use vector minmax expanders for aarch32, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 26/34] target/ppc: Pass integer to helper_mtvscr, Richard Henderson, 2018/12/18