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[Qemu-ppc] [PULL 05/14] 40p: use OR gate to wire up raven PCI interrupts
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 05/14] 40p: use OR gate to wire up raven PCI interrupts |
Date: |
Tue, 25 Sep 2018 17:01:45 +1000 |
From: Mark Cave-Ayland <address@hidden>
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
raven PCI host bridge and then wire the single output of the OR gate to the
interrupt controller.
Note that whilst the (now deprecated) PReP machine still exists we still need
to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
property to the raven PCI host bridge which is set to true for the PReP
machine.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/pci-host/prep.c | 25 +++++++++++++++++++++++--
hw/ppc/prep.c | 4 +---
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 9b36f19c97..b1b6b16bad 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -32,6 +32,7 @@
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
#include "hw/loader.h"
+#include "hw/or-irq.h"
#include "exec/address-spaces.h"
#include "elf.h"
@@ -55,6 +56,7 @@ typedef struct RavenPCIState {
typedef struct PRePPCIState {
PCIHostState parent_obj;
+ qemu_or_irq *or_irq;
qemu_irq pci_irqs[PCI_NUM_PINS];
PCIBus pci_bus;
AddressSpace pci_io_as;
@@ -69,6 +71,7 @@ typedef struct PRePPCIState {
RavenPCIState pci_dev;
int contiguous_map;
+ bool is_legacy_prep;
} PREPPCIState;
#define BIOS_SIZE (1 * MiB)
@@ -222,8 +225,23 @@ static void raven_pcihost_realizefn(DeviceState *d, Error
**errp)
MemoryRegion *address_space_mem = get_system_memory();
int i;
- for (i = 0; i < PCI_NUM_PINS; i++) {
- sysbus_init_irq(dev, &s->pci_irqs[i]);
+ if (s->is_legacy_prep) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ sysbus_init_irq(dev, &s->pci_irqs[i]);
+ }
+ } else {
+ /* According to PReP specification section 6.1.6 "System Interrupt
+ * Assignments", all PCI interrupts are routed via IRQ 15 */
+ s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
+ object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
+ &error_fatal);
+ object_property_set_bool(OBJECT(s->or_irq), true, "realized",
+ &error_fatal);
+ sysbus_init_irq(dev, &s->or_irq->out_irq);
+
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
+ }
}
qdev_init_gpio_in(d, raven_change_gpio, 1);
@@ -382,6 +400,9 @@ static Property raven_pcihost_properties[] = {
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
EM_NONE),
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
+ /* Temporary workaround until legacy prep machine is removed */
+ DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
+ false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index baca1d7c04..4bb831c3e6 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -502,6 +502,7 @@ static void ppc_prep_init(MachineState *machine)
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+ qdev_prop_set_bit(dev, "is-legacy-prep", true);
pcihost = PCI_HOST_BRIDGE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
qdev_init_nofail(dev);
@@ -669,9 +670,6 @@ static void ibm_40p_init(MachineState *machine)
qdev_connect_gpio_out(dev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
- sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
- sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
- sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
/* Memory controller */
--
2.17.1
- [Qemu-ppc] [PULL 00/14] ppc-for-3.1 queue 20180925, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 03/14] hw/ppc: on 40p machine, change default firmware to OpenBIOS, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 06/14] spapr: introduce a spapr_irq class 'nr_msis' attribute, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 02/14] target/ppc/cpu-models: Re-group the 970 CPUs together again, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 05/14] 40p: use OR gate to wire up raven PCI interrupts,
David Gibson <=
- [Qemu-ppc] [PULL 07/14] spapr: increase the size of the IRQ number space, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 04/14] raven: some minor IRQ-related tidy-ups, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 01/14] Record history of ppcemb target in common.json, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 12/14] scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 08/14] spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dt, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 09/14] sm501: Adjust endianness of pixel value in rectangle fill, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 14/14] 40p: add fixed IRQ routing for LSI SCSI device, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 11/14] scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline(), David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 10/14] scsi: add lsi53c8xx_handle_legacy_cmdline() function, David Gibson, 2018/09/25
- [Qemu-ppc] [PULL 13/14] lsi53c895a: add optional external IRQ via qdev, David Gibson, 2018/09/25