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[Qemu-ppc] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHas
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options |
Date: |
Fri, 27 Apr 2018 19:21:17 +1000 |
The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
flag into the PPCHash64Options structure.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/spapr.c | 3 +--
target/ppc/cpu.h | 1 -
target/ppc/kvm.c | 6 +++++-
target/ppc/mmu-hash64.c | 2 +-
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 3 ---
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 9c26dc37e1..abf38c62e8 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineState
*spapr,
void *fdt, int offset,
bool legacy_guest)
{
- CPUPPCState *env = &cpu->env;
uint8_t pa_features_206[] = { 6, 0,
0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
@@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineState
*spapr,
return;
}
- if (env->ci_large_pages) {
+ if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
/*
* Note: we keep CI large pages off by default because a 64K capable
* guest provisioned with large pages might otherwise try to map a qemu
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1c5c33ca11..c0c44fb91d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1090,7 +1090,6 @@ struct CPUPPCState {
#if defined(TARGET_PPC64)
ppc_slb_t vrma_slb;
target_ulong rmls;
- bool ci_large_pages;
#endif
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b53af75ecf..25f93dc708 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
* host page size is smaller than 64K.
*/
if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) {
- env->ci_large_pages = getpagesize() >= 0x10000;
+ if (getpagesize() >= 0x10000) {
+ cpu->hash64_opts->flags |= PPC_HASH64_CI_LARGEPAGE;
+ } else {
+ cpu->hash64_opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
+ }
}
/*
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c9ee55e1ea..f341714550 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
- .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
+ .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index b2b5d25238..f1babb0afc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -155,6 +155,7 @@ struct PPCHash64SegmentPageSizes {
struct PPCHash64Options {
#define PPC_HASH64_1TSEG 0x00001
#define PPC_HASH64_AMR 0x00002
+#define PPC_HASH64_CI_LARGEPAGE 0x00004
unsigned flags;
PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index ae005b2a54..a925cf5cd3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
--
2.14.3
- [Qemu-ppc] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction, (continued)
- [Qemu-ppc] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 30/49] spapr: drop useless dynamic sysbus device sanity check, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 15/49] uninorth: move PCI host bridge bus initialisation into device realize, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 20/49] uninorth: use object link to pass OpenPIC object to uninorth, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 28/49] spapr: drop useless sanity check in spapr_irq_alloc*(), David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 22/49] uninorth: rename UNINState to UNINHostState, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 37/49] target/ppc: Split page size information into a separate allocation, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options,
David Gibson <=
- [Qemu-ppc] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop(), David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 31/49] target/ppc: Standardize instance_init and realize function names, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 23/49] ppc: Fix size of ppc64 xer register, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 27/49] Add host_memory_backend_pagesize() helper, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 25/49] spapr: Introduce pseries-2.13 machine type, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model, David Gibson, 2018/04/27
- [Qemu-ppc] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr(), David Gibson, 2018/04/27