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Re: [Qemu-ppc] [RFC NO-MERGE 08/12] target/ppc: Add POWER9/ISAv3.00 to c
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC NO-MERGE 08/12] target/ppc: Add POWER9/ISAv3.00 to compat_table |
Date: |
Mon, 27 Feb 2017 13:08:05 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Fri, Feb 24, 2017 at 06:06:51PM +1100, Suraj Jitindar Singh wrote:
> On Mon, 2017-02-20 at 13:16 +1100, David Gibson wrote:
> > On Fri, Feb 17, 2017 at 04:08:08PM +1100, Suraj Jitindar Singh wrote:
> > >
> > > compat_table contains the list of logical pvr compat modes which a
> > > cpu can
> > > operate in. It is a list of struct CompatInfo which contains the
> > > given pvr
> > > value for a compat mode, the pcr bits which should be set to
> > > operate in
> > > that compat mode, the pcr level which must be present in
> > > pcr_supported for
> > > a processor to support that compat mode and the max threads
> > > possible in
> > > that compat mode.
> > >
> > > Add an entry for the POWER9/ISAv3.00 logical pvr which represents a
> > > processor running with support for logical pvr 0x0f000005. A
> > > processor
> > > running in this mode should have PCR_COMPAT_3_00 set in the pcr (if
> > > available in pcr_mask) and should have PCR_COMPAT_3_00 in
> > > pcr_supported
> > > to indicate that it is capable of running in this compat mode.
> > >
> > > Also add PCR_COMPAT_3_00 to the bits which must be set for all
> > > previous
> > > compat modes. Since no processor models contain this bit yet in
> > > pcr_mask
> > > it will never be set, but this ensures we don't forget to in the
> > > future.
> > >
> > > Signed-off-by: Suraj Jitindar Singh <address@hidden>
> > > ---
> > > target/ppc/compat.c | 16 +++++++++++-----
> > > 1 file changed, 11 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/target/ppc/compat.c b/target/ppc/compat.c
> > > index 458da26..80c3a95 100644
> > > --- a/target/ppc/compat.c
> > > +++ b/target/ppc/compat.c
> > > @@ -39,29 +39,35 @@ static const CompatInfo compat_table[] = {
> > > */
> > > { /* POWER6, ISA2.05 */
> > > .pvr = CPU_POWERPC_LOGICAL_2_05,
> > > - .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05
> > > - | PCR_TM_DIS | PCR_VSX_DIS,
> > > + .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06
> > > |
> > > + PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
> > > .pcr_level = PCR_COMPAT_2_05,
> > > .max_threads = 2,
> > > },
> > > { /* POWER7, ISA2.06 */
> > > .pvr = CPU_POWERPC_LOGICAL_2_06,
> > > - .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
> > > + .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06
> > > | PCR_TM_DIS,
> > > .pcr_level = PCR_COMPAT_2_06,
> > > .max_threads = 4,
> > > },
> > > {
> > > .pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
> > > - .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
> > > + .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06
> > > | PCR_TM_DIS,
> > > .pcr_level = PCR_COMPAT_2_06,
> > > .max_threads = 4,
> > > },
> > > { /* POWER8, ISA2.07 */
> > > .pvr = CPU_POWERPC_LOGICAL_2_07,
> > > - .pcr = PCR_COMPAT_2_07,
> > > + .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
> > > .pcr_level = PCR_COMPAT_2_07,
> > > .max_threads = 8,
> > > },
> > > + { /* POWER9, ISA3.00 */
> > > + .pvr = CPU_POWERPC_LOGICAL_3_00,
> > > + .pcr = PCR_COMPAT_3_00,
> > > + .pcr_level = PCR_COMPAT_3_00,
> > > + .max_threads = 4,
> > Does this need to be 1 for the time being, until Paulus sorts out the
> > issues about matching guest and host SMT modes.
>
> Good question, I'll check
Actually, I don't think it does, since this is (for now) for the
benefit of TCG guests. The existing mechanism which manipulates the
allowed thread count based on the host for KVM should handle the KVM
case (provided the kernel returns 1 thread max for now, which I
believe it does).
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[Qemu-ppc] [RFC NO-MERGE 11/12] target/ppc: Implement ISA V3.00 radix page fault handler, Suraj Jitindar Singh, 2017/02/17