Re: [Qemu-ppc] [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow

[Richard Henderson]

On 02/23/2017 06:02 PM, Nikunj A Dadhania wrote:
> David Gibson <address@hidden> writes:
>
> > -static void gen_read_xer(TCGv dst)
> > > +static void gen_read_xer(DisasContext *ctx, TCGv dst)
> > >  {
> > >      TCGv t0 = tcg_temp_new();
> > >      TCGv t1 = tcg_temp_new();
> > > @@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
> > >      tcg_gen_or_tl(t0, t0, t1);
> > >      tcg_gen_or_tl(dst, dst, t2);
> > >      tcg_gen_or_tl(dst, dst, t0);
> > > +    if (is_isa300(ctx)) {
> > > +        tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> > > +        tcg_gen_or_tl(dst, dst, t0);
> > > +        tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> > > +        tcg_gen_or_tl(dst, dst, t0);
> >
> > Could you use 2 deposits here, instead of 2 shifts and 2 ors?
>
> I checked the implementation of tcg_gen_deposit_i64, resultant will have much
> more than 2 shifts + 2 ors.

Well, that depends on the host.  For a host that implements deposit, like 
aarch64 or ppc64, it will be one instruction.


r~