[Qemu-ppc] [PATCH v4 15/15] target/ppc: add mcrxrx instruction

[Nikunj A Dadhania]

mcrxrx: Move to CR from XER Extended

Signed-off-by: Nikunj A Dadhania <address@hidden>
---
 target/ppc/translate.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5af9667..f4e41e5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3886,6 +3886,32 @@ static void gen_mcrxr(DisasContext *ctx)
     tcg_temp_free(t0);
 }
 
+#ifdef TARGET_PPC64
+/* mcrxrx */
+static void gen_mcrxrx(DisasContext *ctx)
+{
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
+
+    /* copy OV and OV32 */
+    tcg_gen_extract_tl(t0, cpu_xer, XER_OV_BIT, 1);
+    tcg_gen_extract_tl(t1, cpu_xer, XER_OV32_BIT, 1);
+    tcg_gen_shli_tl(t0, t0, 1);
+    tcg_gen_or_tl(t0, t0, t1);
+    tcg_gen_shli_tl(t0, t0, 1);
+    /* copy CA and CA32 */
+    tcg_gen_extract_tl(t1, cpu_xer, XER_CA_BIT, 1);
+    tcg_gen_or_tl(t0, t0, t1);
+    tcg_gen_shli_tl(t0, t0, 1);
+    tcg_gen_extract_tl(t1, cpu_xer, XER_CA32_BIT, 1);
+    tcg_gen_or_tl(t0, t0, t1);
+    tcg_gen_trunc_tl_i32(dst, t0);
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+}
+#endif
+
 /* mfcr mfocrf */
 static void gen_mfcr(DisasContext *ctx)
 {
@@ -6584,6 +6610,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, 
PPC_MISC),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
 #endif
 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
-- 
2.7.4