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[Qemu-ppc] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add |
Date: |
Wed, 22 Feb 2017 14:59:41 +0530 |
Adds routine to compute ca32 - gen_op_arith_compute_ca32
For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA
and CA32 will have same value.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c9f6768..b589d09 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -816,6 +816,23 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
+static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
+ TCGv res, TCGv arg0, TCGv arg1,
+ int add_ca, int sub)
+{
+ TCGv t0;
+
+ if (!is_isa300(ctx)) {
+ return;
+ }
+
+ t0 = tcg_temp_new();
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ tcg_gen_xor_tl(t0, t0, res);
+ tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
+ tcg_temp_free(t0);
+}
+
/* Common add function */
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, bool add_ca, bool compute_ca,
@@ -842,6 +859,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
} else {
TCGv zero = tcg_const_tl(0);
if (add_ca) {
@@ -850,6 +868,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
} else {
tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
}
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, add_ca, 0);
tcg_temp_free(zero);
}
} else {
--
2.7.4
- [Qemu-ppc] [PATCH v2 00/11] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 01/11] target/ppc: move cpu_[read, write]_xer to cpu.c, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 03/11] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 02/11] target/ppc: optimize gen_write_xer(), Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/22