Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow

[Nikunj A Dadhania]

Richard Henderson <address@hidden> writes:

> On 02/14/2017 02:05 PM, Nikunj A Dadhania wrote:
>> Yes, you are right. I had a discussion with Paul Mackerras yesterday, he
>> explained to me in detail about the bits. I am working on the revised
>> implementation. Will detail it in the commit message.
>
> As you're working on this, consider changing the definition of cpu_ov such 
> that 
> the MSB is OV and bit 31 is OV32.
>
> E.g.
>
>
>   static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
>                                              TCGv arg1, TCGv arg2, int sub)
>   {
>       TCGv t0 = tcg_temp_new();
>
>       tcg_gen_xor_tl(cpu_ov, arg0, arg2);
>       tcg_gen_xor_tl(t0, arg1, arg2);
>       if (sub) {
>           tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
>       } else {
>           tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
>       }
>       tcg_temp_free(t0);
>       if (NARROW_MODE(ctx)) {
>           tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>       }
> -    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>       tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
>   }
>
>
> is all that is required for arithmetic to compute OV and OV32 into those two 
> bits.

How about the below?

@@ -809,10 +809,11 @@ static inline void gen_op_arith_compute_ov(DisasContext 
*ctx, TCGv arg0,
         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
     }
     tcg_temp_free(t0);
+    tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
+    tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
     if (NARROW_MODE(ctx)) {
-        tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
+        tcg_gen_mov_tl(cpu_ov, cpu_ov32);
     }
-    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 }

Regards
Nikunj