Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
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Tested the corner cases for round-to-odd and the default round-to-nearest-even
by comparing the results of QEMU with a known good implementation of
PowerPC ISA 3.0 for the following instructions: xsaddqp[o], xsdivqp[o],
xsmulqp[o] and xscvqpdp[o].
Changes in v3:
- Limited the recalculation of roundIncrement in 64bit rounding only
to round-to-odd case and hence dropped the separate patch which
did this for all rounding modes earlier. (Peter Maydell)
- Resorted to QEMU codying style in softfloat.c