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[Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u,
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp |
Date: |
Thu, 2 Feb 2017 16:14:25 +1100 |
From: Bharata B Rao <address@hidden>
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was
introduced in ppc_vsr_t. Now that we have it, use it instead of
generating the 128 bit float using two 64bit fields.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ae57272..d648234 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2452,8 +2452,8 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
exp_a = extract64(xa.VsrD(0), 48, 15);
exp_b = extract64(xb.VsrD(0), 48, 15);
- if (unlikely(float128_is_any_nan(make_float128(xa.VsrD(0), xa.VsrD(1))) ||
- float128_is_any_nan(make_float128(xb.VsrD(0), xb.VsrD(1))))) {
+ if (unlikely(float128_is_any_nan(xa.f128) ||
+ float128_is_any_nan(xb.f128))) {
cc = CRF_SO;
} else {
if (exp_a < exp_b) {
@@ -2528,24 +2528,20 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
ppc_vsr_t xa, xb; \
uint32_t cc = 0; \
bool vxsnan_flag = false, vxvc_flag = false; \
- float128 a, b; \
\
helper_reset_fpstatus(env); \
getVSR(rA(opcode) + 32, &xa, env); \
getVSR(rB(opcode) + 32, &xb, env); \
\
- a = make_float128(xa.VsrD(0), xa.VsrD(1)); \
- b = make_float128(xb.VsrD(0), xb.VsrD(1)); \
- \
- if (float128_is_signaling_nan(a, &env->fp_status) || \
- float128_is_signaling_nan(b, &env->fp_status)) { \
+ if (float128_is_signaling_nan(xa.f128, &env->fp_status) || \
+ float128_is_signaling_nan(xb.f128, &env->fp_status)) { \
vxsnan_flag = true; \
cc = CRF_SO; \
if (fpscr_ve == 0 && ordered) { \
vxvc_flag = true; \
} \
- } else if (float128_is_quiet_nan(a, &env->fp_status) || \
- float128_is_quiet_nan(b, &env->fp_status)) { \
+ } else if (float128_is_quiet_nan(xa.f128, &env->fp_status) || \
+ float128_is_quiet_nan(xb.f128, &env->fp_status)) { \
cc = CRF_SO; \
if (ordered) { \
vxvc_flag = true; \
@@ -2558,9 +2554,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
} \
\
- if (float128_lt(a, b, &env->fp_status)) { \
+ if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \
cc |= CRF_LT; \
- } else if (!float128_le(a, b, &env->fp_status)) { \
+ } else if (!float128_le(xa.f128, xb.f128, &env->fp_status)) { \
cc |= CRF_GT; \
} else { \
cc |= CRF_EQ; \
--
2.9.3
- [Qemu-ppc] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, (continued)
- [Qemu-ppc] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 107/107] hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 103/107] tcg/POWER9: NOOP the cp_abort instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp,
David Gibson <=
- [Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 092/107] powerpc/cpu-models: rename ISAv3.00 logical PVR definition, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 091/107] target-ppc: Add xvcv[hpsp, sphp] instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 071/107] host-utils: Implement unsigned quadword left/right shift and unit tests, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 076/107] target-ppc: Add xsiexpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 083/107] target-ppc: Add xscvqps[d, w]z instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 104/107] target/ppc/mmu_hash64: Fix printing unsigned as signed int, David Gibson, 2017/02/02