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[Qemu-ppc] [PULL 056/107] target-ppc: Add xsxexpdp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 056/107] target-ppc: Add xsxexpdp instruction |
Date: |
Thu, 2 Feb 2017 16:13:54 +1100 |
From: Nikunj A Dadhania <address@hidden>
xsxexpdp: VSX Scalar Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 13 +++++++++++++
target/ppc/translate/vsx-ops.inc.c | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 2a409a3..33ca177 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1213,6 +1213,19 @@ static void gen_##name(DisasContext *ctx)
\
VSX_EXTRACT_INSERT(xxextractuw)
VSX_EXTRACT_INSERT(xxinsertw)
+#ifdef TARGET_PPC64
+static void gen_xsxexpdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(rt, rt, 0x7FF);
+}
+#endif
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 5c01aed..85d3b7d 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -113,6 +113,10 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08,
0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
+#ifdef TARGET_PPC64
+GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+#endif
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 069/107] softfloat: Fix the default qNAN for target-ppc, (continued)
- [Qemu-ppc] [PULL 069/107] softfloat: Fix the default qNAN for target-ppc, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 049/107] prep: add IBM RS/6000 7020 (40p) memory controller, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 067/107] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 029/107] target-ppc: implement stxvl instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 043/107] hw/ppc: QOM'ify e500.c, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 035/107] ppc: Rewrite ppc_get_compat_smt_threads(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 030/107] target-ppc: implement stxvll instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 046/107] target-ppc: Add xxextractuw instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 040/107] qtest: convert ivshmem-test to use libqos, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 058/107] target-ppc: Add xsxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 056/107] target-ppc: Add xsxexpdp instruction,
David Gibson <=
- [Qemu-ppc] [PULL 041/107] qtest: add ivshmem-test for ppc64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 048/107] prep: add PReP System I/O, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 068/107] target-ppc: xscvqpdp zero VSR, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 052/107] target-ppc: Replace isden by float64_is_zero_or_denormal, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 070/107] host-utils: Move 128-bit guard macro to .c file, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 063/107] target-ppc: Add xsaddqp instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 054/107] target-ppc: Add xscvdphp, xscvhpdp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 061/107] pseries: Rewrite CAS PVR compatibility logic, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 050/107] prep: add IBM RS/6000 7020 (40p) machine emulation, David Gibson, 2017/02/02