Re: [Qemu-ppc] [PATCH v6] target-ppc: Implement mtvsrws instruction

[David Gibson]

On Thu, Sep 29, 2016 at 09:22:17AM +0530, Nikunj A Dadhania wrote:
> From: Ravi Bangoria <address@hidden>
> 
> mtvsrws: Move To VSR Word & Splat
> 
> Signed-off-by: Ravi Bangoria <address@hidden>
> Signed-off-by: Nikunj A Dadhania <address@hidden>

Looks ok to me, applied to ppc-for-2.8.

> ---
>  target-ppc/translate/vsx-impl.inc.c | 19 +++++++++++++++++++
>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>  2 files changed, 20 insertions(+)
> 
> diff --git a/target-ppc/translate/vsx-impl.inc.c 
> b/target-ppc/translate/vsx-impl.inc.c
> index 4120c01..23ec1e1 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -384,6 +384,25 @@ static void gen_mtvsrdd(DisasContext *ctx)
>      tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);
>  }
>  
> +static void gen_mtvsrws(DisasContext *ctx)
> +{
> +    if (xT(ctx->opcode) < 32) {
> +        if (unlikely(!ctx->vsx_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VSXU);
> +            return;
> +        }
> +    } else {
> +        if (unlikely(!ctx->altivec_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VPU);
> +            return;
> +        }
> +    }
> +
> +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)],
> +                        cpu_gpr[rA(ctx->opcode)], 32, 32);
> +    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode)));
> +}
> +
>  #endif
>  
>  static void gen_xxpermdi(DisasContext *ctx)
> diff --git a/target-ppc/translate/vsx-ops.inc.c 
> b/target-ppc/translate/vsx-ops.inc.c
> index c49ba6d..10eb4b9 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -28,6 +28,7 @@ GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, 
> PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
>  GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
>  #endif
>  
>  #define GEN_XX1FORM(name, opc2, opc3, fl2)                              \

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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