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Re: [Qemu-ppc] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions |
Date: |
Thu, 29 Sep 2016 12:25:27 +1000 |
User-agent: |
Mutt/1.7.0 (2016-08-17) |
On Wed, Sep 28, 2016 at 11:15:18AM +0530, Rajalakshmi Srinivasaraghavan wrote:
> The following vector instructions are added from ISA 3.0.
>
> vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
> vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte
>
> Signed-off-by: Rajalakshmi Srinivasaraghavan
> <address@hidden>
This will do for now, but I think you could do better than the loop.
Something like:
tmp = vector & 0x0101010101010101;
count = (clz(tmp) + 1) >> 3;
I think would do it (obviously more care would be needed with edge cases).
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/int_helper.c | 28 ++++++++++++++++++++++++++++
> target-ppc/translate/vmx-impl.inc.c | 14 ++++++++++++++
> target-ppc/translate/vmx-ops.inc.c | 2 ++
> 4 files changed, 46 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9c3095f..30c4429 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -343,6 +343,8 @@ DEF_HELPER_2(vpopcntb, void, avr, avr)
> DEF_HELPER_2(vpopcnth, void, avr, avr)
> DEF_HELPER_2(vpopcntw, void, avr, avr)
> DEF_HELPER_2(vpopcntd, void, avr, avr)
> +DEF_HELPER_1(vclzlsbb, tl, avr)
> +DEF_HELPER_1(vctzlsbb, tl, avr)
> DEF_HELPER_3(vbpermd, void, avr, avr, avr)
> DEF_HELPER_3(vbpermq, void, avr, avr, avr)
> DEF_HELPER_2(vgbbd, void, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index f132f7b..759ead9 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -881,6 +881,34 @@ VCT(uxs, cvtsduw, u32)
> VCT(sxs, cvtsdsw, s32)
> #undef VCT
>
> +target_ulong helper_vclzlsbb(ppc_avr_t *r)
> +{
> + target_ulong count = 0;
> + int i;
> + VECTOR_FOR_INORDER_I(i, u8) {
> + if (r->u8[i] & 0x01) {
> + break;
> + }
> + count++;
> + }
> + return count;
> +}
> +target_ulong helper_vctzlsbb(ppc_avr_t *r)
> +{
> + target_ulong count = 0;
> + int i;
> +#if defined(HOST_WORDS_BIGENDIAN)
> + for (i = ARRAY_SIZE(r->u8) - 1; i >= 0; i--) {
> +#else
> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> +#endif
> + if (r->u8[i] & 0x01) {
> + break;
> + }
> + count++;
> + }
> + return count;
> +}
> void helper_vmhaddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
> ppc_avr_t *b, ppc_avr_t *c)
> {
> diff --git a/target-ppc/translate/vmx-impl.inc.c
> b/target-ppc/translate/vmx-impl.inc.c
> index 0bc7188..1649b34 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -691,6 +691,18 @@ static void glue(gen_, name)(DisasContext *ctx)
> \
> tcg_temp_free_ptr(rd); \
> }
>
> +#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> + { \
> + TCGv_ptr rb; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
> + tcg_temp_free_ptr(rb); \
> + }
> GEN_VXFORM_NOA(vupkhsb, 7, 8);
> GEN_VXFORM_NOA(vupkhsh, 7, 9);
> GEN_VXFORM_NOA(vupkhsw, 7, 25);
> @@ -905,6 +917,8 @@ GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
> GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
> GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
> GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
> +GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
> +GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
> GEN_VXFORM_NOA(vpopcntb, 1, 28)
> GEN_VXFORM_NOA(vpopcnth, 1, 29)
> GEN_VXFORM_NOA(vpopcntw, 1, 30)
> diff --git a/target-ppc/translate/vmx-ops.inc.c
> b/target-ppc/translate/vmx-ops.inc.c
> index 009e9b1..20d243f 100644
> --- a/target-ppc/translate/vmx-ops.inc.c
> +++ b/target-ppc/translate/vmx-ops.inc.c
> @@ -223,6 +223,8 @@ GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
> GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
> GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
> GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
> +GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0),
> +GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1),
> GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
>
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions, (continued)